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參數(shù)資料
| 型號： | IDT728980PDG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 256X256 40-DIP |
| 標準包裝： | 9 |
| 系列： | 7200 |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 8:8 |
| 獨立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP |
| 包裝： | 管件 |
| 其它名稱： | 728980PDG |
3
Commercial Temperature Range
IDT728980 Time Slot Interchange
Digital Switch 256 x 256
is split into two 8-bit blocks—Connection Memory HIGH and Connection
Memory LOW. Each location in Connection Memory is associated with a
particularchannelintheoutputstreamsoastoprovideaone-to-onecorrespon-
dencebetweenthetwomemories. Thiscorrespondenceallowsforperchannel
control for each TX output stream. In Processor Mode, data output on the TX
stream is taken from the Connect Memory Low and originates from the
microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is
read from Data Memory using the address in Connection Memory. Data
destined for a particular channel on the serial output stream is read during the
previouschanneltimeslottoallowtimeformemoryaccessandinternalparallel-
to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connect Memory Low. The Connect Memory Low locations
are mapped to corresponding 8-bit x 32-channel output. The contents of the
Data Memory at the selected address are then transferred to the parallel-to-
serial converters. By having the output channel to specify the input channel
throughtheconnectmemory,inputchannelscanbebroadcasttoseveraloutput
channels.
PROCESSOR MODE
In Processor Mode the CPU writes data to specific Connect Memory Low
locationswhicharetobeoutputontheTXstreams. ThecontentsoftheConnect
Memory Low are transferred to the parallel-to-serial converter one channel
before it is to be output and are transmitted each frame to the output until it is
changed by the CPU.
CONTROL
The Connect Memory High bits (Table 4) control the per-channel functions
available in the IDT728980. Output channels are selected into specific modes
such as: Processor Mode or Connection mode and Output Drivers Enabled
or in three-state condition. There is also one bit to control the state of the CCO
outputpin.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master output control pin. If the ODE input is held LOW
all TDM outputs will be placed in high impedance regardless Connect Memory
Highprogramming. However,ifODEisHIGH,thecontentsofConnectMemory
High control the output state on a per-channel basis.
DELAY THROUGH THE IDT728980
The transfer of information from the input serial streams to the output serial
streamsresultsinadelaythroughthedevice. ThedelaythroughtheIDT728980
devicevariesaccordingtothecombinationofinputandoutputstreamsandthe
movementwithinthestreamfromchanneltochannel. Datareceivedonaninput
stream must first be stored in Data Memory before it is sent out.
As information enters the IDT728980 it must first pass through an internal
serial-to-parallel converter. Likewise, before data leaves the device, it must
passthroughtheinternalparallel-to-serialconverter.Thisdatapreparationhas
an effect on the channel positioning in the frame immediately following the
incoming frame-mainly, data cannot leave in the same time slot, or in the time
slotimmediatelyfollowing. Therefore,informationthatistobeoutputinthesame
channel position as the information is input, relative to the frame pulse, will be
output in the following frame. As well, information switched to the channel
immediately following the input channel will not be output in the time slot
immediatelyfollowing,butinthenexttimeslotallocatedtotheoutputchannel,one
framelater.
Whether information can be output during a following timeslot after the
information entered the IDT728980 depends on which RX stream the channel
information enters on and which TX stream the information leaves on. This is
causedbytheorderinwhichinputstreaminformationisplacedintoDataMemory
and the order in which stream information is queued for output. Table 1 shows
theallowableinput/outputstreamcombinationsfortheminimum2channeldelay.
SO.TWARE CONTROL
If the A5 address line input is LOW then the IDT728980 Internal Control
Register is addressed. If A5 input line is high, then the remaining address input
linesareusedtoselectthe32possiblechannelsperinputoroutputstream. The
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT728980 Data and
Connection memories. The IDT728980 memory mapping is illustrated in
Table 2 and Figure 3.
The data in the control register (Table 3) consists of Memory Select and
Stream Address bits, Split Memory and Processor Mode bits. In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connect Memory as specified by the Memory Select Bits (Bits 4 and
3 of the Control Register). The Memory Select bits allow the Connect Memory
High or LOW or the Data Memory to be chosen, and the Stream Address bits
define internal memory subsections corresponding to input or output streams.
The Processor Enable bit (bit 6) places EVERY output channel on every
outputstreaminProcessorMode;i.e.,thecontentsoftheConnectMemoryLOW
(CML, see Table 5) are output on the TX output streams once every frame
unlesstheODEinputpinisLOW.IfPEbitisHIGH,thentheIDT728980behaves
as if bits 2 (Channel Source) and 0 (Output Enable) of every Connect Memory
High (CMH) locations were set to HIGH, regardless of the actual value. If PE
is LOW, then bit 2 and 0 of each Connect Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
theCMLdefinethesourceinformation(streamandchannel)ofthetimeslotthat
is to be switched to an output.
5706 drw06
TX
Microprocessor
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
5706 drw05
RX
TX
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Figure 2. Processor Mode
Figure 1. Connection Mode
.UNCTIONAL DESCRIPTION (Cont'd)
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| IDT728981DB | 功能描述:IC DGTL SW 128X128 44-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器 系列:7200 標準包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| IDT728981DBG | 功能描述:IC DGTL SW 128X128 44-PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器 系列:7200 標準包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| IDT728981J | 功能描述:IC DGTL SW 256X256 44-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器 系列:7200 標準包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| IDT728981J8 | 功能描述:IC DGTL SW 256X256 44-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號開關(guān)，多路復(fù)用器，解碼器 系列:7200 標準包裝:48 系列:74VHC 類型:多路復(fù)用器 電路:4 x 2:1 獨立電路:1 輸出電流高，低:8mA，8mA 電壓電源:單電源 電源電壓:2 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
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