IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9," />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� IDT72851L10TF8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 14/16闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO SYNC DUAL 8192X9 64QFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,250
绯诲垪锛� 7200
鍔熻兘锛� 鍚屾
瀛樺劜(ch菙)瀹归噺锛� 72K锛�4K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 100MHz
瑷晱鏅�(sh铆)闁擄細 10ns
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 64-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 64-TQFP锛�10x10锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72851L10TF8
7
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
LDA
LDA WENA1
WENA1
WCLKA
OPERATION ON FIFO A
LDB
LDB WENB1
WENB1
WCLKB
OPERATION ON FIFO B
00
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
NoOperation
1
0
Write Into FIFO
1
NoOperation
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
Figure 2. Writing to Offset Registers for FIFOs A and B
A read and write should not be performed simultaneously to the offset
registers.
OUTPUTS:
Full Flag (FFA, FFB) 鈥� FFA (FFB) will go LOW, inhibiting further write
operations,when ArrayA(B)isfull. Ifnoreadsareperformedafterreset,FFA
(FFB) will go LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes
totheIDT72811'sFIFOA(B);1,024writestotheIDT72821'sFIFOA(B);2,048
writes to the IDT72831's FIFO A (B); 4,096 writes to the IDT72841's FIFO A
(B); or 8,192 writes to the IDT72851's FIFO A (B).
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionofthe
WriteClockWCLKA(WCLKB).
EmptyFlag(EFA, EFB)鈥擡FA(EFB)willgoLOW,inhibitingfurtherread
operations,whenthereadpointerisequaltothewritepointer,indicatingthat
Array A (B) is empty.
EFA(EFB)is synchronizedwithrespecttotheLOW-to-HIGHtransitionof
the Read Clock RCLKA (RCLKB).
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72801 - DUAL 256 x 9
72811 - DUAL 512 x 9
7
80
(MSB)
1
00
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72831 - DUAL 2,048 x 9
72851 - DUAL 8,192 x 9
7
80
(MSB)
0
2
(MSB)
0
3
80
(MSB)
0
2
(MSB)
0
3
80
8
0
80
(MSB)
1
0
3034 drw 04
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72841 - DUAL 4,096 x 9
7
80
(MSB)
0
4
80
(MSB)
0
4
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
72821 - DUAL 1,024 x 9
7
80
(MSB)
0
1
80
(MSB)
0
1
NOTE:
1. For the purposes of this table, WENA2 and WENB2 = VIH.
2. The same selection sequence applies to reading from the registers. RENA1 and
RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-to-
HIGH transition of RCLKA (RCLKB).
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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