
10
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
Figure 6. Read Cycle Timing
tENH
tENS
NO OPERATION
tOLZ
VALID DATA
tSKEW1
(1)
tCLK
tCLKH
tCLKL
tREF
tA
tOE
tOHZ
RCLKA (RCLKB)
RENA1, RENA2
(
RENB1, RENB2)
EFA (EFB)
QA0 - QA8
(QB0 - QB8)
OEA (OEB)
WCLKA (WCLKB)
WENA1 (WENB1)
WENA2 (WENB2)
3034 drw 07
tDS
D0 (First Valid Write)
tSKEW1
D0
D1
D3
D2
D1
tENS
tFRL
(1)
tREF
tA
tOLZ
tOE
tA
WCLKA (WCLKB)
DA0 - DA8
(DB0 - DB8)
WENA2 (WENB2)
(If Applicable)
RCLKA (RCLKB)
EFA (EFB)
RENA1, RENA2
(
RENB1, RENB2)
QA0 - QA8
(QB0 - QB8)
OEA (OEB)
WENA1 (WENB1)
3034 drw 08
tENS
NOTE:
1. When tSKEW1
≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1
< minimum specification, tFRL = 2tCLK + tSKEW1V or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 7. First Data Word Latency Timing