IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9" />
參數(shù)資料
型號(hào): IDT72831L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 7/16頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC DUAL 2048X9 64-TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 7200
功能: 同步
存儲(chǔ)容量: 18.4K(2K x 9)
數(shù)據(jù)速率: 67MHz
訪問時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72831L15PF8
15
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
accordingtotype,sendingonekindtoFIFOAandtheotherkindtoFIFOB.Then,
at theoutputs,eachdatatypeistransferredtoitsappropriatedestination.Additional
IDT72801/72811/72821/72831/72841/72851s permit more than two priority
levels.Prioritybufferingisparticularlyusefulinnetworkapplications.
TWO PRIORITY DATA BUFFER
CONFIGURATION
The two FIFOs contained in the IDT72801/72811/72821/72831/72841/
72851canbeusedtoprioritizetwodifferenttypesofdatasharedonasystembus.
When writing from the bus to the FIFO, control logic sorts the intermixed data
Figure 16. Block Diagram of Two Priority Configuration
BIDIRECTIONAL CONFIGURATION
The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can
be used to buffer data flow in two directions. In the example that follows, a
processor can write data to a peripheral controller via FIFO A, and, in turn,
the peripheral controller can write the processor via FIFO B.
Figure 17. Block Diagram of Bidirectional Configuration
RAM ARRAY A
Processor
Data
DA0-DA8
QA0-QA8
OEA
RENA
Address
IDT
72801
72811
72821
72831
72841
72851
DB0-DB8
QB0-QB8
OEB2
WENB1
Control
Logic
RAM
9-bit
bus
RCLKA
WCLKB
Control
9
WCLKA
WENA1
RAM ARRAY B
RENB1
Clock
RCLKB
WENB2
RENB2
WENA2
RENA2
VCC
9
Voice Processing
Card
Data
I/O Data
Clock
Control
Logic
Address
Control
Image Processing
Card
Data
I/O Data
Clock
Control
Logic
Address
Control
3034 drw 17
RAM ARRAY A
Processor
Peripheral
Controller
Data
DA0-DA8
QA0-QA8
Data
OEA
RENA1
Address
I/O Data
IDT
72801
72811
72821
72831
72841
72851
DB0-DB8
QB0-QB8
OEB
WENB1
RAM
9-bit
bus
9-bit
bus
RCLKA
WCLKB
Control
9
WCLKA
WENA1
RAM ARRAY B
RENB1
Clock
RCLKB
DMA Clock
Control
Logic
Address
Control
9
WENB2
RENB2
WENA2 RENA2
VCC
3034 drw 18
Control
Logic
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