IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOT" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72825LB15PF
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 5/26闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO SYNC DL 1024X18 128TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 72
绯诲垪锛� 7200
鍔熻兘锛� 鍚屾
瀛樺劜瀹归噺锛� 18.4K锛�1K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 67MHz
瑷晱鏅傞枔锛� 15ns
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 128-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 128-TQFP锛�14x20锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 72825LB15PF
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
JANUARY 13, 2009
Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then
EF may not change state until the next RCLK edge.
2. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)
NO OPERATION
RCLK
REN
EF
tCLK
tCLKH
tCLKL
tENS
tENH
tREF
VALID DATA
tA
tOLZ
tOE
tOHZ
Q0 - Q17
OE
WCLK
WEN
tSKEW1
(1)
3139 drw 07
WCLK
D0 - D17
WEN
RCLK
EF
Q0 - Q17
REN
tDS
tSKEW1
tENS
tREF
tA
0
12
3
D
DDD
01
DD
(first valid write)
tOE
tOLZ
OE
tA
tFRL
(1)
D4
tENS
3139 drw 08
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing
applies only at the Empty Boundary (
EF = LOW).
2. The first word is available the cycle after
EF goes HIGH, always.
3. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
IDT72825LB15PF8 鍔熻兘鎻忚堪:IC FIFO SYNC DL 1024X18 128TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72825LB15PFGI 鍒堕€犲晢:Integrated Device Technology Inc 鍔熻兘鎻忚堪:IC FIFO SYNC DL 1024X18 128TQFP
IDT72825LB15PFGI8 鍒堕€犲晢:Integrated Device Technology Inc 鍔熻兘鎻忚堪:IC FIFO SYNC DL 1024X18 128TQFP
IDT72825LB15PFI 鍔熻兘鎻忚堪:IC FIFO SYNC DL 1024X18 128TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
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