IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOT" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� IDT72825LB10PF8
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋佹暩(sh霉)锛� 18/26闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO SYNC DL 1024X18 128TQFP
妯欐簴鍖呰锛� 1,000
绯诲垪锛� 7200
鍔熻兘锛� 鍚屾
瀛樺劜瀹归噺锛� 18.4K锛�1K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 100MHz
瑷晱鏅傞枔锛� 10ns
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 128-LQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 128-TQFP锛�14x20锛�
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� 72825LB10PF8
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
JANUARY 13, 2009
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
3139 drw 31
n
RXI
HF
72805
72815
72825
72835
72845
WXI
FL
VCC
GND
(0,1)
72805
72815
72825
72835
72845
RXI
WXI
FL
VCC
GND
(0,1)
PAF
HF
PAE
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72805LB/72815LB/72825LB/72835LB/
72845LB devices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next (鈥渞ipple down鈥�) until
it finally appears at the outputs of the last FIFO in the chain鈥搉o read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device鈥檚
OR line goes LOW, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
OR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO鈥檚 outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N 鈥� 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between WCLK and transfer clock, or RCLK
and transfer clock, for the
OR flag.
The 鈥渞ipple down鈥� delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will 鈥渂ubble up鈥� from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO鈥檚
IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for
IR of the
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
(N 鈥� 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specification is not met between RCLK and transfer clock, or WCLK
and transfer clock, for the
IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
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MS27484T14F35SC CONN PLUG 37POS STRAIGHT W/SCKT
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MS27484T14F35SD CONN PLUG 37POS STRAIGHT W/SCKT
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
IDT72825LB10PFG 鍔熻兘鎻忚堪:IC FIFO 1024X18 SYNC DL 128TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯欐簴鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅傞枔:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳鍟嗚ō鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
IDT72825LB10PFG8 鍒堕€犲晢:Integrated Device Technology Inc 鍔熻兘鎻忚堪:IC FIFO SYNC DL 1024X18 128TQFP
IDT72825LB15BG 鍔熻兘鎻忚堪:IC FIFO SYNC DL 1024X18 121BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯欐簴鍖呰:15 绯诲垪:74F 鍔熻兘:鐣版 瀛樺劜瀹归噺:256锛�64 x 4锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱鏅傞枔:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:24-DIP锛�0.300"锛�7.62mm锛� 渚涙噳鍟嗚ō鍌欏皝瑁�:24-PDIP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:74F433
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