- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗10038 > IDT72801L10PF (IDT, Integrated Device Technology Inc)IC FIFO SYNC DUAL 256X9 64-TQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | IDT72801L10PF |
| 寤犲晢锛� | IDT, Integrated Device Technology Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/16闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FIFO SYNC DUAL 256X9 64-TQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | 7200 |
| 鍔熻兘锛� | 鍚屾 |
| 瀛樺劜(ch菙)瀹归噺锛� | 2.3K锛�256 x 9锛� |
| 鏁�(sh霉)鎿�(j霉)閫熺巼锛� | 100MHz |
| 瑷晱鏅�(sh铆)闁擄細 | 10ns |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 64-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 64-TQFP锛�14x14锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鍏跺畠鍚嶇ū锛� | 72801L10PF |
3
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
MARCH 2013
Symbol
Name
I/O
Description
DA0-DA8
ADataInputs
I
9-bit data inputs to RAM array A.
DB0-DB8
BDataInputs
I
9-bit data inputs to RAM array B.
RSA
, RSB
Reset
I
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to
the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go
LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.
WCLKA
WriteClock
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write
WCLKB
enable(s) are asserted.
WENA1
WriteEnable1
I
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only Write
WENB1
Enable pin that can be used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO
on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables,
WENA1
(WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if FFA (FFB) is LOW.
WENA2/LDA
WriteEnable2/
I
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB)
WENB2/LDB
Load
is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA (WENB2/LDB) is LOW
at reset this pin operates as a control to load and read the programmable flag offsets for its respective array.
If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW
and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)
if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA (LDB) is held LOW to write or
readtheprogrammableflagoffsets.
QA0-QA8
ADataOutputs
O
9-bit data outputs from RAM array A.
QB0-QB8
BDataOutputs
O
9-bit data outputs from RAM array B.
RCLKA
Read Clock
I
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1
RCLKB
(RENB1) and RENA2 (RENB2) are asserted.
RENA1
Read Enable 1
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every
RENB1
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
RENA2
Read Enable 2
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every
RENB2
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA(EFB) is LOW.
OEA
OutputEnable
I
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the
OEB
outputs DA0-DA8 (DB0-DB8) will be in a high-impedance state.
EFA
EmptyFlag
O
When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.
EFB
When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
PAEA
Programmable
O
When PAEA (PAEB) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the
PAEB
Almost-Empty
appropriate offset register. The default offset at reset is Empty+7. PAEA(PAEB) is synchronized to
Flag
RCLKA (RCLKB).
PAFA
Programmable
O
When PAFA(PAFB) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate
PAFB
Almost-FullFlag
offset register. The default offset at reset is Full-7. PAFA(PAFB) is synchronized to WCLKA (WCLKB).
FFA
Full Flag
O
When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.
FFB
When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
VCC
Power
+5V power supply pin.
GND
Ground
0V ground pin.
PIN DESCRIPTIONS
The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred
to as FIFO A and FIFO B, are identical in every respect. The following
description defines the input and output signals for FIFO A. The correspond-
ing signal names for FIFO B are provided in parentheses.
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| IDT72801L10PF8 | 鍔熻兘鎻忚堪:IC FIFO SYNC DUAL 256X9 64-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯�(bi膩o)婧�(zh菙n)鍖呰:80 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜(ch菙)瀹归噺:18.4K锛�1K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱鏅�(sh铆)闁�:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�10x10锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72225LB10TF |
| IDT72801L10PFG | 鍔熻兘鎻忚堪:IC FIFO SYNC DUAL 256X9 64-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜(ch菙)瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅�(sh铆)闁�:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF |
| IDT72801L10PFG8 | 鍔熻兘鎻忚堪:IC FIFO SYNC DUAL 256X9 64-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯�(bi膩o)婧�(zh菙n)鍖呰:80 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜(ch菙)瀹归噺:18.4K锛�1K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱鏅�(sh铆)闁�:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�10x10锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72225LB10TF |
| IDT72801L10TF | 鍔熻兘鎻忚堪:IC FIFO SYNC DUAL 256X9 64QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜(ch菙)瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱鏅�(sh铆)闁�:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF |
| IDT72801L10TF8 | 鍔熻兘鎻忚堪:IC FIFO SYNC DUAL 256X9 64QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:7200 妯�(bi膩o)婧�(zh菙n)鍖呰:80 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜(ch菙)瀹归噺:18.4K锛�1K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱鏅�(sh铆)闁�:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�10x10锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72225LB10TF |
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