參數(shù)資料
型號: IDT72615L25J8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 8/17頁
文件大小: 0K
描述: IC FIFO BY SYNC 512X18X2 68PLCC
標(biāo)準(zhǔn)包裝: 250
系列: 7200
功能: 同步
存儲容量: 18.4K(512 x 18 x 2)
數(shù)據(jù)速率: 40MHz
訪問時(shí)間: 25ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24x24)
包裝: 帶卷 (TR)
其它名稱: 72615L25J8
16
INDUSTRIALTEMPERATURERANGE
IDT72605/72615 CMOS SYNCBiFIFO
256 x 18x 2 and 512 x 18 x 2
Full - m words in FIFO
WRITE
(2)
Full - (m+1) words in FIFO
tCLKL
2704 drw 18
CLKB
ENB
(R/
WA = 0)
PAFBA
CLKA
ENA
(R/
WA = 1)
tCLKH
tCS
tCH
tPAF
tCS
tCH
tSKEW2
(1)
tPAF
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 15. B
→A Programmable Almost-Full Flag Timing
(1)
WRITE
READ
n words in FIFO
n+1 words in FIFO
tCLKL
2704 drw 17
CLKB
ENB
(R/
WA = 0)
PAEBA
CLKA
ENA
(R/
WA = 1)
tCLKH
tCS
tCH
tPAE
tCS
tCH
tSKEW2
tPAE
(2)
Figure 14. B
→A Programmable Almost-Empty Flag Timing
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
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