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參數(shù)資料
| 型號(hào)： | IDT72403L25P |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO PAR 64X4 25NS 16-DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | 7200 |
| 功能： | 異步 |
| 存儲(chǔ)容量： | 256（64 x 4） |
| 數(shù)據(jù)速率： | 25MHz |
| 訪問(wèn)時(shí)間： | 25ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 72403L25P |
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
8
JUNE 29, 2012
NOTES:
1. When the memory is empty, the last word will remain on the outputs until the MR is strobed or a new data word falls through to the output. However, OR will remain LOW,
indicating data at the output is not valid.
2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data
has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.
3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one
internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the
first word and will not appear on the outputs until SO has been brought LOW.
4. When the MR is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the MR goes HIGH, the data on the inputs will be
written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the MR is ended, IR will go HIGH, but the data in the inputs will not
enter the memory until SI goes HIGH.
5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR flags. This is due to the
variation of delays of the FIFOs.
Figure 11. 192 x 12 Depth and Width Expansion
2747 drw 15
IR
SI
SO
OR
SI
IR
OR
SO
SI
IR
OR
SO
SI
IR
OR
SO
SHIFT OUT
COMPOSITE
OUTPUT
READY
MR
SHIFT IN
COMPOSITE
INPUT
READY
IR
SI
SO
OR
IR
SI
SO
OR
IR
SI
SO
OR
IR
SI
SO
OR
IR
SI
SO
OR
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
MR
Q0
Q1
Q2
Q3
D0
D1
D2
D3
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| IDT72403L25SO | 功能描述:IC FIFO PAR 64X4 25NS 16-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤(pán) 其它名稱(chēng):72225LB10TF |
| IDT72403L25SO8 | 功能描述:IC FIFO PAR 64X4 25NS 16-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤(pán) 其它名稱(chēng):72225LB10TF |
| IDT72403L35DB | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO ASYNC 64X4 35NS 16CDIP |
| IDT72403L35P | 功能描述:IC FIFO PAR 64X4 35NS 16-DIP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤(pán) 其它名稱(chēng):72225LB10TF |
| IDT72403L35S0 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Async Dual Depth/Width Uni-Dir 64 x 4 16-Pin SOIC Tube |
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