![](http://datasheet.mmic.net.cn/IDT--Integrated-Device-Technology-Inc/IDT723653L15PF8_datasheet_105029/IDT723653L15PF8_8.png)
8
COMMERCIALTEMPERATURERANGE
IDT723653/723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Commercial
IDT723653L12
IDT723653L15
IDT723663L12
IDT723663L15
IDT723673L12
IDT723673L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
—
83
—
66.7
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
12
—
15
—
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
5
—
6
—
ns
tCLKL
Pulse Duration, CLKA and CLKB LOW
5
—
6
—
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and B0-B35 before CLKB↑
3—
4
—
ns
tENS1
Setup Time,
CSAand W/RAbefore CLKA
↑; CSBand W/RB before CLKB↑
4
—
4.5
—
ns
tENS2
Setup Time, ENA, and MBA before CLKA
↑; ENB and MBB before CLKB↑
3
—
4.5
—
ns
tRSTS
Setup Time,
RS1or PRSLOW before CLKA
↑ or CLKB↑(1)
5—
5
—
ns
tFSS
Setup Time, FS0, FS1 and FS2 before
RS1 HIGH
7.5
—
7.5
—
ns
tBES
Setup Time, BE/
FWFTbefore RS1HIGH
7.5
—
7.5
—
ns
tSDS
Setup Time, FS0/SD before CLKA
↑
3—
4
—
ns
tSENS
Setup Time, FS1/
SENbefore CLKA
↑
3—
4
—
ns
tFWS
Setup Time, FWFT before CLKA
↑
0—
0
—
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and B0-B35 after CLKB↑
0.5
—
1
—
ns
tRTMS
Setup Time, RTM before
RT1; RTM before RT2
5—
5
—
ns
tENH
Hold Time,
CSA, W/RA, ENA, and MBA after CLKA
↑; CSB, W/RB, ENB,
0.5
—
1
—
ns
and MBB after CLKB
↑
tRSTH
Hold Time,
RS1or PRSLOW after CLKA
↑ or CLKB↑(1)
4—
4
—
ns
tFSH
Hold Time, FS0, FS1 and FS2 after
RS1 HIGH
2
—
2
—
ns
tBEH
Hold Time, BE/
FWFT after RS1HIGH
2
—
2
—
ns
tSDH
Hold Time, FS0/SD after CLKA
↑
0.5
—
1
—
ns
tSENH
Hold Time, FS1/
SENHIGH after CLKA
↑
0.5
—
1
—
ns
tSPH
Hold Time, FS1/
SEN HIGH after RS1HIGH
2
—
2
—
ns
tRTMH
Hold Time, RTM after
RT1; RTM after RT2
5—
5
—
ns
tSKEW1(2)
Skew Time between CLKA
↑ and CLKB↑ for EF/OR and FF/IR
5
—
7.5
—
ns
tSKEW2(2,3)
Skew Time between CLKA
↑ and CLKB↑ for AE and AF
12
—
12
—
ns
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
4. Industrial temperature range is available by special order.
(Commercial: VCC = 5V ± 10%, TA = 0
°C to +70°C)