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參數(shù)資料
| 型號： | IDT723642L15PQFGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 20/25頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 2048X36 132QFP |
| 標準包裝： | 36 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 72K（2K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 供應商設備封裝： | 132-PQFP（24.13x24.13） |
| 包裝： | 托盤 |
| 其它名稱： | 723642L15PQFGI |
4
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/0
36-bit bidirectional data port for side A.
AEA
Port A Almost-
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words
Empty Flag
(Port A)
in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB
Port B Almost-
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words
Empty Flag
(Port B)
in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA
Port A Almost-
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
Full Flag
(Port A)
locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFB
Port B Almost-
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
Full Flag
(Port B)
locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0 - B35
Port B Data
I/O
36-bit bidirectional data port for side B.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. IRA, ORA,
AFA, and AEA are all synchronized to the
LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. IRB, ORB,
AFB, and AEB are synchronized to the LOW-
to-HIGH transition of CLKB.
CSA
Port A Chip
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A.
Select
The A0-A35 outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on
Select
port B. The B0-B35 outputs are in the high-impedance state when
CSB is HIGH.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FS1, FS0
FlagOffset
I
The LOW-to-HIGH transition of a FlFO’s Reset input latches the values of FS0 and FS1.
Selects
If either FS0 or FS1 is HIGH when a Reset goes HIGH, one of three preset values is selected as
the offset for the FlFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously
and both FS0 and FS1 are LOW when
RST1 and RST2 go HIGH, the first four writes to FIFO1
load the Almost-Empty and Almost-Full offsets for both FlFOs.
IRA
Input Ready
O
IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is LOW, FIFO1 is full
Flag
(Port A)
and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the
second LOW-to-HIGH transition of CLKA after reset.
IRB
Input Ready
O
IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is LOW, FIFO2 is full
Flag
(Port B)
and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the
second LOW-to-HIGH transition of CLKB after reset.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation.
Select
When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for
output and a LOW level selects FIFO2 output register data for output.
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
Select
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and
a LOW level selects FIFO1 output register data for output.
MBF1
Mail1 Register
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1
Flag
register. Writes to the mail1 register are inhibited while
MBF1 is LOW. MBF1 is set HIGH by
a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH.
MBF1 is
set HIGH when FIFO1 is reset.
MBF2
Mail2 Register
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Flag
Writes to the mail2 register are inhibited while
MBF2 is LOW. MBF2 is set HIGH by a LOW-
to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH.
MBF2 is also
set HIGH when FIFO2 is reset.
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| IDT723643L12PF | 功能描述:IC FIFO SYNC 1024X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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