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參數(shù)資料
| 型號(hào)： | IDT723631L20PFI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 21/21頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 512X36 120-TQFP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 18.4K（512 x 36） |
| 數(shù)據(jù)速率： | 50MHz |
| 訪問時(shí)間： | 20ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723631L20PFI8 |
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1,024 x 36 and 2,048 x 36
9
When the option to program the Offset registers serially is chosen, the
Input Ready (IR) flag remains LOW until all register bits are written. The IR
flag is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is
loaded to allow normal FIFO operation. Timing diagrams for the serial load
of offset registers can be found in Figure 4.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled by the port-A
Chip Select (
CSA) and the port-A Write/Read select (W/RA). The A0-A35
outputs are in the high-impedance state when either
CSA or W/RA is
HIGH. The A0-A35 outputs are active when both
CSA and W/RA are
LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA and the port-A Mailbox select (MBA) are
LOW, W/
RA, the port-A Enable (ENA), and the Input Ready (IR) flag are
HIGH (see Table 2). Writes to the FIFO are independent of any concur-
rent FIFO read (see Figure 5).
The port-B control signals are identical to those of port-A with the excep-
tion that the port-B Write/Read select (
W/RB) is the inverse of the port-A
Write/Read select (W/
RA). The state of the port-B data (B0-B35) outputs is
controlled by the port-B Chip Select (
CSB) and the port-B Write/Read
select (
W/RB). The B0-B35 outputs are in the high-impedance state when
either
CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active
when
CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to its output register on a LOW-to-HIGH
transition of CLKB when
CSB and the port-B Mailbox select (MBB) are
LOW,
W/RB, the port-B Enable (ENB), and the Output Ready (OR) flag
are HIGH (see Table 3). Reads from the FIFO are independent of any
concurrent FIFO writes (see Figure 6).
The setup- and hold-time constraints to the port clocks for the port Chip
Selects and Write/Read selects are only for enabling write and read op-
erations and are not related to high-impedance control of the data outputs.
If a port Enable is LOW during a clock cycle, the port Chip Select and
Write/Read select may change states during the setup- and hold time
window of the cycle.
When the OR flag is LOW, the next data word is sent to the FIFO output
register automatically by the CLKB LOW-to-HIGH transition that sets the
OR flag HIGH. When OR is HIGH, an available data word is clocked to the
FIFO output register only when a FIFO read is selected by the port-B
Chip Select (
CSB), Write/Read select (W/RB), Enable (ENB), and Mailbox
select (MBB).
SYNCHRONIZED FIFO FLAGS
Each IDT723631/723641/723651 FIFO flag is synchronized to its port
Clock through at least two flip-flop stages. This is done to improve the flags’
reliability by reducing the probability of metastable events on their outputs
SIGNALDESCRIPTION
RESET
The IDT723631/723641/723651 is reset by taking the Reset (
RST)
input LOW for at least four port-A Clock (CLKA) and four port-B (CLKB)
LOW-to-HIGH transitions. The Reset input may switch asynchronously to
the clocks. A reset initializes the memory read and write pointers and
forces the Input Ready (IR) flag LOW, the Output Ready (OR) flag LOW,
the Almost-Empty (
AE) flag LOW, and the Almost-Full (AF) flag HIGH.
Resetting the device also forces the Mailbox Flags (
MBF1, MBF2) HIGH.
After a FIFO is reset, its Input Ready flag is set HIGH after at least two
clock cycles to begin normal operation. A FIFO must be reset after power
up before data is written to its memory.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET
PROGRAMMING
Two registers in these devices are used to hold the offset values for the
Almost-Empty and Almost-Full flags. The Almost-Empty (
AE) flag Offset
register is labeled X, and the Almost-Full (
AF) flag Offset register is labeled
Y. The Offset register can be loaded with a value in three ways: one of two
preset values are loaded into the Offset registers, parallel load from port A,
or serial load. The Offset register programming mode is chosen by the flag
select (FS1, FS0) inputs during a LOW-to-HIGH transition on the
RST
input (See Table 1).
PRESET VALUES
If the preset value of 8 or 64 is chosen by the FS1 and FS0 inputs at the
time of a
RST LOW-to-HIGH transition according to Table 1, the preset
value is automatically loaded into the X and Y registers. No other device
initialization is necessary to begin normal operation, and the IR flag is set
HIGH after two LOW-to-HIGH transitions on CLKA. For relevant Reset and
Preset value loading timing diagrams, see Figure 2.
PARALLEL LOAD FROM PORT A
To program the X and Y registers from port A, the device is reset with
FS0 and FS1 LOW during the LOW-to-HIGH transition of
RST. After this
reset is complete, the IR flag is set HIGH after two LOW-to-HIGH transitions
on CLKA. The first two writes to the FIFO do not store data in its memory
but load the Offset registers in the order Y, X. Each Offset register of the
IDT723631, IDT723641, and IDT723651 uses port-A inputs (A8-A0), (A9-
A0), and (A10-A0), respectively. The highest number input is used as the
most significant bit of the binary number in each case. Each register value
can be programmed from 1 to 508 (IDT723631), 1 to 1,020 (IDT723641),
and 1 to 2,044 (IDT723651). After both Offset registers are programmed
from port A, subsequent FIFO writes store data in the SRAM. Timing
diagrams for the parallel load of offset registers can be found in Figure 3.
SERIAL LOAD
To program the X and Y registers serially, the device is reset with FS0/
SD and FS1/
SEN HIGH during the LOW-to-HIGH transition of RST. After
this reset is complete, the X and Y register values are loaded bitwise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that
the FS1/
SEN input is LOW. There are 18-, 20-, or 22-bit writes needed to
complete the programming for the IDT723631, IDT723641, or IDT723651,
respectively. The first-bit write stores the most significant bit of the Y regis-
ter, and the last-bit write stores the least significant bit of the X register.
Each register value can be programmed from 1 to 508 (IDT723631), 1 to
1,020 (IDT723641), or 1 to 2,044 (IDT723651).
NOTE:
1. X register holds the offset for
AE; Y register holds the offset for AF.
FS1
FS0
RST
X and Y Registers (1)
HH
↑
Serial Load
HL
↑
64
LH
↑
8
LL
↑
Parallel Load From Port A
TABLE 1 — FLAG PROGRAMMING
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