參數(shù)資料
型號(hào): IDT723624L12PFG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 33/35頁(yè)
文件大小: 0K
描述: IC FIFO 256X36X2 SYNC 128TQFP
標(biāo)準(zhǔn)包裝: 72
系列: 7200
功能: 同步
存儲(chǔ)容量: 18.4K(256 x 36 x 2)
數(shù)據(jù)速率: 83MHz
訪問(wèn)時(shí)間: 12ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
7
COMMERCIALTEMPERATURERANGE
IDT723624/723634/723644 CMOS SyncBiFIFO WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723624/723634/723644 with
CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data
outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number
of IDT723624/723634/723644 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x
ICC x dc)] + Σ(CL x VCC2 X fo)
where:
N
=
number of used outputs = 36-bit (long word), 18-bit (word) or 9-bit (byte) bus size
ICC
=
increase in power supply current for each input at a TTL HIGH level
dc
=
duty cycle of inputs at a TTL HIGH level of 3.4 V
CL
=
outputcapacitanceload
fo
=
switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010
20
30
40
50
60
70
0
50
100
250
300
VCC = 5.0V
fS
Clock Frequency MHz
fdata = 1/2 fS
TA = 25
°C
CL = 0pF
VCC = 5.5V
3270 drw03
200
150
VCC = 4.5V
80
90
ICC(f)
Supply
Current
mA
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IDT723624L12PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 256X36X2 128QFP
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