參數(shù)資料
型號: IDT72285L15TF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/25頁
文件大?。?/td> 0K
描述: IC FIFO 65536X18 LP 15NS 64STQFP
標準包裝: 80
系列: 7200
功能: 同步
存儲容量: 1.1M(65K x 18)
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 72285L15TF
13
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275/72285
CMOS SuperSync FIFO 32,768 x 18 and 65,536 x 18
(65,536-m)writesfortheIDT72285.Theoffset“m”isthefulloffsetvalue.The
defaultsettingforthisvalueisstatedinthefootnoteofTable1.
InFWFTmode,thePAFwillgoLOWafter(32,769-m)writesfortheIDT72275
and (65,537-m) writes for the IDT72285, where m is the full offset value. The
defaultsettingforthisvalueisstatedinthefootnoteofTable2.
SeeFigure16,ProgrammableAlmost-FullFlagTiming(IDTStandardand
FWFTMode),fortherelevanttiminginformation.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
whentherearenwordsorless in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (HF)
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF will go LOW after ((D/2) + 1) writes to the FIFO, where D = 32,768 for the
IDT72275 and 65,536 for the IDT72285.
InFWFTmode,ifnoreadsareperformedafterreset(MRSorPRS),HFwill
go LOW after ((D-1)/2 + 2) writes to the FIFO, where D = 32,769 for the
IDT72275 and 65,537 for the IDT72285.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
WCLK,itisconsideredasynchronous.
DATAOUTPUTS(Q0-Q17)
(Q0 - Q17) are data outputs for 18-bit wide data.
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