Figure 8. Read Cycle, Empty Flag and Fi" />
參數(shù)資料
型號(hào): IDT72285L10PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 8/25頁
文件大小: 0K
描述: IC FIFO 65536X18 LP 10NS 64-TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 7200
功能: 同步
存儲(chǔ)容量: 1.1M(65K x 18)
訪問時(shí)間: 10ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72285L10PF8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275/72285
CMOS SuperSync FIFO 32,768 x 18 and 65,536 x 18
16
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle plus tWFF). If the time
between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
D0 - Dn
WEN
RCLK
FF
REN
tENH
Q0 - Qn
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
tSKEW1
(1)
4674 drw10
WCLK
1
2
1
2
tDS
tWFF
tA
tENS
tSKEW1
(1)
tDS
tA
DX
tDH
tCLKH
DX+1
tWFF
tDH
tCLK
tCLKL
NO WRITE
RCLK
REN
4674 drw 11
EF
tCLKH
tCLKL
tENH
tREF
tA
tOLZ
tOE
Q0 - Qn
OE
WCLK
(1)
tSKEW3
WEN
D0 - Dn
tENS
tENH
tDS
tDHS
D0
1
2
tOLZ
LAST WORD
D0
D1
tENS
tENH
tDS
tDH
tOHZ
LAST WORD
tREF
tENH
tENS
tA
tENS
tENH
tCLK
tREF
NO OPERATION
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IDT72285L10PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 65536X18 LP 10NS 64-TQFP
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