
19
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72281/72291
CMOS SuperSync FIFO 65,536 x 9 and 131,072 x 9
Figure
10.
Read
Timing
(First
Word
Fall
Through
Mode)
WCLK
12
WEN
D
0
-
D
8
RCLK
tENS
REN
Q
0
-Q
8
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
tOHZ
tSKEW1
tENH
tDS
tDH
tOE
tA
tPAF
tWFF
tENS
OE
tSKEW2
W
D
4675
drw
13
tPAE
W
[D-n]
W
[D-n-1]
tA
tHF
tREF
W
[D-1]
W
D
tA
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
tENS
D-1
]
[
W
D-1
]
[
W
NOTES:
1.
t
SKEW1
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
IR
will
go
LOW
after
one
WCLK
cycle
plus
t
WFF
.If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
t
SKEW1
,then
the
IR
assertion
may
be
delayed
one
extra
WCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
PAF
will
go
HIGH
after
one
WCLK
cycle
plus
t
PAF
.If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
t
SKEW2
,then
the
PAF
deassertion
may
be
delayed
one
extra
WCLK
cycle.
3.
LD
=
HIGH.
4.
n=
PAE
Offset,
m
=
PAF
offset
and
D
=
maximum
FIFO
depth.
5.
D
=
65,537
for
the
IDT72281
and
131,073
for
the
IDT72291.