參數(shù)資料
型號: IDT72261LA20TFI8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 17/27頁
文件大?。?/td> 0K
描述: IC FIFO 8192X18 LP 20NS 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 7200
功能: 同步
存儲容量: 144K(8K x 18)
數(shù)據(jù)速率: 50MHz
訪問時(shí)間: 20ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72261LA20TFI8
24
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72261LA/72271LA SuperSync FIFO
16,384 x 9 and 32,768 x 9
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
The exceptions are the EF and FF functions in IDT Standard mode and the
IR andOR functions in FWFT mode. Because of variations in skew between
RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR assertion
to vary by one cycle between FIFOs. In IDT Standard mode, such problems
Figure 19. Block Diagram of 16,384 x 18 and 32,768 x 18 Width Expansion
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (
MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (
WEN)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE (
PAF)
PROGRAMMABLE (
PAE)
EMPTY FLAG/OUTPUT READY (
EF/OR) #2
OUTPUT ENABLE (
OE)
READ ENABLE (
REN)
m
LOAD (
LD)
IDT
72261LA
72271LA
EMPTY FLAG/OUTPUT READY (
EF/OR) #1
PARTIAL RESET (
PRS)
IDT
72261LA
72271LA
4671 drw 22
FULL FLAG/INPUT READY (
FF/IR) #2
HALF-FULL FLAG (
HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (
RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
canbeavoidedbycreatingcompositeflags,thatis,ANDingEFofeveryFIFO,
and separately ANDing FF of every FIFO. In FWFT mode, composite flags
canbecreatedbyORingORofeveryFIFO,andseparatelyORingIRofevery
FIFO.
Figure 21 demonstrates a width expansion using two IDT72261LA/
72271LA devices. D0 - D8 from each device form a 18-bit wide input bus and
Q0-Q8 from each device form a 18-bit wide output bus. Any word width can
be attained by adding additional IDT72261LA/72271LA devices.
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