5 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 IDT72255LA IDT72265LA ADDENDUM DIFFERENCES BETWEEN" />
參數(shù)資料
型號(hào): IDT72255LA15PF
廠(chǎng)商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 20/27頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 8KX18 LP 15NS 64QFP
標(biāo)準(zhǔn)包裝: 90
系列: 7200
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
訪(fǎng)問(wèn)時(shí)間: 15ns
電源電壓: 4 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 托盤(pán)
其它名稱(chēng): 72255LA15PF
27
5 VOLT CMOS SuperSync FIFO
8,192 x 18
16,384 x 18
IDT72255LA
IDT72265LA
ADDENDUM
DIFFERENCES BETWEEN THE IDT72255LA/72265LA AND IDT72255L/72265L
IDT has improved the performance of the IDT72255/72265 SuperSync FIFOs. The new versions are designated by the “LA” mark. The LA part is pin-
for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.
Item
NEW PART
OLD PART
Comments
IDT72255LA
IDT72255L
IDT72265LA
IDT72265L
Pin #3
DC (Don’t Care) - There is
FS (Frequency Select)
In the LA part this pin must be tied
no restriction on WCLK and
to either VCC or GND and must
RCLK. See note 1.
not toggle after reset.
First Word Latency
60ns(2) + tREF + 1 TRCLK(4)
tFWL1 = 10*Tf(3) + 2TRCLK(4)(ns)
First word latency in the LA part is
(IDT Standard Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
First Word Latency
60ns(2) + tREF + 2 TRCLK(4)
tFWL2 = 10*Tf(3) + 3TRCLK(4)(ns)
First word latency in the LA part is
(FWFT Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit Latency
60ns(2) + tREF + 1 TRCLK(4)
tRTF1 = 14*Tf(3) + 3TRCLK(4)(ns)
Retransmit latency in the LA part is
(IDT Standard Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
Retransmit Latency
60ns(2) + tREF + 2 TRCLK(4)
tRTF2 = 14*Tf(3) + 4TRCLK(4)(ns)
Retransmit latency in the LA part is
(FWFT Mode)
a fixed value, independent of the
frequency of RCLK or WCLK.
ICC1
80mA
180mA
Active supply current
ICC2
20mA
15mA
Standby current
Typical ICC1(5)
15 + 2.1*fS + 0.02*CL*fS(mA)
Not Given
Typical ICC1 Current calculation
NOTES:
1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.
2. This is tSKEW3.
3. Tf is the period of the ‘selected clock’.
4. TRCLK is the cycle period of the read clock.
5. Typical ICC1 is based on VCC = 5V, tA = 25
°C, fS = WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2, CL = Capacitive Load (in pF).
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
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IDT72255LA15PFGI 功能描述:IC FIFO 8KX18 LP 15NS 64QFP RoHS:是 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪(fǎng)問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF
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IDT72255LA15PFI 功能描述:IC FIFO 8KX18 LP 15NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪(fǎng)問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF