參數(shù)資料
型號(hào): IDT72210L15TP
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 11/11頁(yè)
文件大小: 0K
描述: IC FIFO 512X8 SYNC 15NS 28-DIP
標(biāo)準(zhǔn)包裝: 14
系列: 7200
功能: 同步
存儲(chǔ)容量: 4K (512 x 8)
數(shù)據(jù)速率: 67MHz
訪問時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 28-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 28-PDIP
包裝: 管件
其它名稱: 72210L15TP
9
COMMERCIALTEMPERATURERANGE
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
NOTES:
1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the current clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge.
2. If a write is performed on this rising edge of the Write Clock, there will be Full -7 words in the FIFO when AF goes LOW.
Figure 8. Almost Full Flag Timing
NOTES:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the current clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge.
2. If a read is performed on this rising edge of the Read Clock, there will be Empty +7 words in the FIFO when AE goes LOW.
Figure 9. Almost Empty Flag Timing
WCLK
WEN
tENS
AE
tENH
tCLKH
tCLKL
tAE
RCLK
REN
tENS
Empty+7
Empty+8
tSKEW2
(1)
tENH
(2)
tAE
2680 drw 11
WCLK
WEN
tENS
AF
tENH
tCLKH
tCLKL
RCLK
REN
tENS
tSKEW2
(1)
Full - 8 words in FIFO
Full - 7 words in FIFO
(2)
tAF
tENH
2680 drw10
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