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參數(shù)資料
| 型號： | IDT72125L50TP |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 1KX16 PAR-SER 28DIP |
| 標(biāo)準(zhǔn)包裝： | 14 |
| 系列： | 7200 |
| 功能： | 異步 |
| 存儲容量： | 16K (1K x 16) |
| 訪問時間： | 50ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 28-PDIP |
| 包裝： | 管件 |
| 其它名稱： | 72125L50TP |
7
INDUSTRIAL TEMPERATURE RANGE
IDT72105/72115/72125 PARALLEL-TO-SERIAL CMOS FIFO
256 x 16, 512 x 16, 1,024 x 16
Figure 8. Half-Full, Almost-Full and Almost-Empty Timings
2665 drw 10
SOCP
tWPF
0
SO
DATA IN
DATA IN VALID
1
n–1
tSOCFF
tWFF
tDS
tDH
tSOPD
NOTE 1
DATA OUT VALID
2665 drw 11
SOCP
tWF
HALF-FULL (1/2)
HALF-FULL
7/8 FULL
ALMOST-EMPTY
(1/8 FULL – 1)
ALMOST-EMPTY
(1/8 FULL – 1)
tWF
ALMOST-FULL (7/8 FULL + 1)
1/8 FULL
HALF-FULL + 1
tSOCF
Figure 7. Full Boundary Condition Timing
NOTE:
1.
Single Device Mode will not tri-state but will retain the last valid data.
NOTES:
1.
Once
EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
2.
In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.
Figure 6. Empty Boundary Condition Timing
2665 drw 09
SOCP
tREFSO
tWEF
0
1
n–1
SO
DATA IN
tSOCEF
tSOLZ
tSOPD
NOTE 1
NOTE 2
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