參數資料
型號: IDT7202LA50P
廠商: IDT, Integrated Device Technology Inc
文件頁數: 2/14頁
文件大?。?/td> 0K
描述: IC FIFO ASYNCH 1KX9 35NS 28DIP
標準包裝: 13
系列: 7200
功能: 異步
存儲容量: 9K(1K x 9)
數據速率: 15MHz
訪問時間: 50ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 28-DIP(0.600",15.24mm)
供應商設備封裝: 28-PDIP
包裝: 管件
其它名稱: 7202LA50P
800-2477-5
IDT7202LA50P-ND
10
COMMERCIAL,INDUSTRIALANDMILITARY
TEMPERATURERANGES
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
USAGE MODES:
WIDTH EXPANSION
Word width may be increased simply by connecting the corresponding
inputcontrolsignalsofmultipledevices. Statusflags(EF,FFandHF)canbe
detectedfromanyonedevice. Figure13demonstratesan18-bitwordwidth
by using two IDT7200/7201A/7202As. Any word width can be attained by
adding additional IDT7200/7201A/7202As (Figure 13).
BIDIRECTIONAL OPERATION
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT7200/7201A/7202As as shown in Figure 16. Both Depth Expansion and
Width Expansion may be used in this mode.
DATA FLOW-THROUGH
Two types of flow-through modes are permitted, a read flow-through
and write flow-through mode. For the read flow-through mode (Figure 17),
theFIFOpermitsareadingofasinglewordafterwritingonewordofdatainto
anemptyFIFO. Thedataisenabledonthebusin(tWEF+tA)nsaftertherising
edgeofW,calledthefirstwriteedge,anditremainsonthebusuntiltheRline
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after tRHZ ns. The EF line would have a pulse showing temporary
deassertion and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing
of a single word of data immediately after reading one word of data from a
fullFIFO. TheRlinecausestheFFtobedeassertedbuttheWlinebeingLOW
causesittobeassertedagaininanticipationofanewdataword. Ontherising
edge of W, the new word is loaded in the FIFO. The W line must be toggled
whenFFisnotassertedtowritenewdataintheFIFOandtoincrementthewrite
pointer.
COMPOUND EXPANSION
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode
Figure 12. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9 FIFO
WRITE (
W)
DATA IN (D)
FULL FLAG (
FF)
RESET (
RS)
9
READ (
R)
9
DATA OUT (Q)
EMPTY FLAG (
EF)
RETRANSMIT (
RT)
EXPANSION IN (
XI)
(
HF)
IDT
7200/
7201A/
7202A
(HALF-FULL FLAG)
2679 drw 14
IDT
7200/
7201A/
7202A
XI
99
18
9
18
HF
9
DATA
WRITE (
W)
FULL FLAG (
FF)
RESET (
RS)
(D)
IN
READ (
R)
EMPTY FLAG (
EF)
RETRANSMIT (
RT)
DATA OUT (Q)
IDT
7200/
7201A/
7202A
2679 drw 15
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