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參數(shù)資料
| 型號： | IDT71V802S133BGI |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect |
| 中文描述： | 256 × 36，為512k × 18 3.3同步SRAM的2.5VI / O的脈沖計數(shù)器輸出流水線，單周期取消 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 988K |
| 代理商： | IDT71V802S133BGI |
DECEMBER 2003
DSC-5311/07
1
2002 Integrated Device Technology, Inc.
A
0
-A
18
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS
0
,
CS
1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power I/O Power
Supply
N/A
V
SS
Ground
Supply
N/A
5311 tbl 01
Features
N
256K x 36, 512K x 18 memory configurations
N
Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
N
LBO
input selects interleaved or linear burst mode
N
Self-timed write cycle with global write control (
write enable (
BWE
), and byte writes (
N
3.3V core power supply
N
Power down controlled by ZZ input
N
2.5V I/O supply (V
DDQ
)
N
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array.
GW
), byte
BW
x)
Pin Description Summary
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V67802.
256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
IDT71V67602
IDT71V67802
Description
The IDT71V67602/7802 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAMto generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
systemdesigner, as the IDT71V676
02
/78
02
can provide four cycles of
data for a single address presented to the SRAM An internal burst address
counter accepts the first cycle address fromthe processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (
ADV
=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the
LBO
input pin.
The IDT71V67602/7802 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mmx 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
相關(guān)PDF資料 |
PDF描述 |
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| IDT71V802S133BQ | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect |
| IDT71V802S133BQI | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect |
| IDT71V802S133PF | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect |
| IDT71V802S133PFI | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect |
| IDT71V802S150BG | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect |
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| IDT7200L12J8 | 功能描述:IC MEM FIFO 256X9 12NS 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT7200L12JG | 功能描述:IC MEM FIFO 256X9 12NS 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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