
6.15
8
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES:
1. Timing depends on which signal is asserted last,
CE
,
OE
,
LB
, or
UB
.
2. Timing depends on which signal is de-asserted first,
CE
,
OE
,
LB
, or
UB
.
3. t
BDD
delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last
t
ABE
, t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
TIMING OF POWER-UP POWER-DOWN
WAVEFORM OF READ CYCLES
(5)
t
RC
R/
W
CE
ADDR
t
AA
t
ACE(4)
OE
UB
,
LB
2740 drw 07
(4)
t
AOE(4)
t
ABE(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3, 4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
2740 drw 08
t
PU
I
CC
I
SB
t
PD
50%
50%