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參數(shù)資料
| 型號(hào)： | IDT7024L17PFB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 高速4K的× 16 DUAL-PORT靜態(tài)RAM |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 292K |
| 代理商： | IDT7024L17PFB |
6.15
6
IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(Cont.)
(V
CC
= 5.0V
±
10%)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7024X35
7024X55
Mil. Only
Test
Symbol
I
CC
Parameter
Condition
Version
MIL.
Typ.
(2)
150
150
150
150
13
13
13
13
85
85
85
85
1.0
0.2
1.0
0.2
Max.
300
250
250
210
80
65
60
50
190
160
155
130
30
10
15
5
Typ.
(2)
150
150
150
150
13
13
13
13
85
85
85
85
1.0
0.2
1.0
0.2
Max. Typ.
(2)
300
250
250
210
80
65
60
50
190
160
155
130
30
10
15
5
Max. Unit
300
250
—
—
80
65
—
—
190
160
—
—
30
10
—
—
Dynamic Operating
Current
(Both Ports Active)
CE
= V
IL
, Outputs Open
SEM
= V
IH
f = f
MAX(3)
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
140
140
—
—
10
10
—
—
80
80
—
—
1.0
0.2
—
—
mA
COM’L.
I
SB1
Standby Current
(Both Ports — TTL
Level Inputs)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX(3)
MIL.
mA
COM’L.
I
SB2
Standby Current
(One Port — TTL
Level Inputs)
CE
"A"
=V
IL and
CE
"B"
=V
IH(5)
Active Port Outputs Open
f = f
MAX(3)
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2 and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V,
Active Port Outputs Open,
f = f
MAX(3)
MIL.
mA
COM’L.
I
SB3
Full Standby Current
(Both Ports — All
CMOS Level Inputs)
MIL.
mA
COM’L.
I
SB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
MIL.
S
L
80
80
175
150
80
80
175
150
75
75
175
150
mA
COM’L.
S
L
80
80
135
110
80
80
135
110
—
—
—
—
NOTES:
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25
°
C, and are not production tested. I
CCDC
= 120
mA
(typ.)
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycleof 1/tRC, and using “AC Test Conditions”of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2740 tbl 10
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
(4)
Symbol
Parameter
Test Condition
Min.
Typ.
(1)
Max.
Unit
V
DR
I
CCDR
V
CC
for Data Retention
Data Retention Current
V
CC
= 2V
CE
> V
HC
V
IN
> V
HC
or < V
LC
SEM
> V
HC
2.0
—
—
0
t
RC(2)
—
100
100
—
—
—
V
μ
A
MIL.
COM’L.
4000
1500
—
—
t
CDR(3)
R(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
ns
ns
NOTES:
1. T
A
= +25
°
C, V
CC
= 2V, and are by characterization but are not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed by device characterization but are not production tested.
4
.
At Vcc < 2.0V, input leakages are not defined.
DATA RETENTION WAVEFORM
2740 tbl 11
DATA RETENTION MODE
V
CC
CE
2740 drw 05
4.5V
t
CDR
t
R
V
IH
V
DR
V
IH
4.5V
V
DR
2V
≥
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