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參數(shù)資料
| 型號： | IDT70125S55JG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 2K X 9 DUAL-PORT SRAM, 55 ns, PQCC52 |
| 封裝： | 0.75 X 0.75 INCH, 0.17 INCH HEIGHT, GREEN, PLASTIC, LCC-52 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70125S55JG |
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
AC Elec tric al Charac teristic s Over the
Operating Temperature and S upply Voltage Range
(3)
APRIL 05, 2006
NOTES:
1. Transition is measured 0mV fromLow or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Unit
Symbol
Parameter
Mn.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
25
____
35
____
ns
t
AA
Address Access Time
____
25
____
35
ns
t
ACE
Chip Enable Access Time
____
25
____
35
ns
t
AOE
Output Enable Access Time
____
12
____
25
ns
t
OH
Output Hold fromAddress Change
0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
15
ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50
ns
2654 tbl 09a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Unit
Symbol
Parameter
Mn.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
45
____
55
____
ns
t
AA
Address Access Time
____
45
____
55
ns
t
ACE
Chip Enable Access Time
____
45
____
55
ns
t
AOE
Output Enable Access Time
____
30
____
35
ns
t
OH
Output Hold fromAddress Change
0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
30
ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50
ns
2654 tbl 09b
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70125S55JGI | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125L55J | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125S25J | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125S35J | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125S45J | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70125S55JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125S55L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70125S55L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70125S70L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT7012L25C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
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