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| 型號： | IDT70125L45JGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 高速2K × 9雙端口靜態(tài)RAM繁忙 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70125L45JGI |
7
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
T iming Waveform of Read Cycle No. 1, Either S ide
(1,2,4)
APRIL 05, 2006
NOTES:
1. Timng depends on which signal is aserted last,
OE
or
CE
.
2. Timng depends on which signal is deaserted first,
OE
or
CE
.
3.
t
BDD
delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relationship to valid output data.
4. Start of valid data depends on which timng becomes effective last,
t
AOE,
t
ACE,
t
AA, or
t
BDD.
5. R/
W
= V
IH
,
CE
= V
IL
, and
OE
= V
IL
, and the address is valid prior to other coincidental with
CE
transition LOW.
T iming Waveform of Read Cycle No. 2, Either S ide
(5)
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2654 drw 05
t
BDD
(3,4)
BUSY
OUT
CE
t
ACE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2654 drw 06
(4)
(1)
(1)
(2)
(2)
(4)
t
LZ
t
HZ
t
AOE
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| IDT70125L55JG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
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