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參數(shù)資料
| 型號： | IDT70125L25JG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 2K X 9 DUAL-PORT SRAM, 25 ns, PQCC52 |
| 封裝： | 0.75 X 0.75 INCH, 0.17 INCH HEIGHT, GREEN, PLASTIC, LCC-52 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70125L25JG |
9
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
T iming Waveform of Write Cycle No. 1, R/
W
Controlled T iming
(1,5,8)
t
WC
APRIL 05, 2006
NOTES:
1. R/
W
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
= V
IL
and a R/
W
= V
IL
3. t
WR
is measured fromthe earlier of
CE
or R/
W
going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
LOW transition occurs simultaneously with or after the R/
W
LOW transition, the outputs remain in the High-impedance state.
6. Timng depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is determned be device characterization, but is not production tested. Transition is measured 0mV fromsteady state with the Output Test Load
(Figure 2).
8. If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be
placed on the bus for the required t
DW
. If
OE
is HIGH during a R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
WP
.
T iming Waveform of Write Cycle No. 2,
CE
Controlled T iming
(1,5)
R/
W
t
HZ
t
AW
t
HZ
t
AS
t
WP
DATA
OUT
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE
t
WZ
(4)
(4)
t
WR
2654 drw 07
(3)
(7)
(2)
(6)
(7)
(7)
CE
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
2654 drw 08
(6)
(2)
(3)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70125L25JG8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 18KBIT 25NS 52PLCC |
| IDT70125L25JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70125L25L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70125L35J | 功能描述:IC SRAM 18KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT70125L35J8 | 功能描述:IC SRAM 18KBIT 35NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應商設備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
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