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參數(shù)資料
| 型號： | IDT70121S55JGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 高速2K × 9雙端口靜態(tài)RAM繁忙 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70121S55JGI |
13
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
T iming Waveform of Interrupt Mode
(1)
APRIL 05, 2006
Truth Tables
Truth Table II. Interrupt Flag
(1,4)
Truth Table I. Non-Contention Read/Write Control
(4)
NOTES:
1. A
0L
– A
10L
≠
A
0R
– A
10R
.
2. If
BUSY
= L, data is not written.
3. If
BUSY
= L, data may not be valid, see t
WDD
and t
DDD
timng.
4. 'H' = V
IH
, 'L' = V
IL
, 'X' = DONT CARE, 'Z' = HIGH IMPEDANCE
NOTES
:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
2. If BUSY
L
= V
IL
, then No Change.
3. If BUSY
R
= V
IL
, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DONT CARE
t
INS
ADDR
'A'
INT
'B'
INTERRUPT SET ADDRESS
t
WC
t
AS
R/
W
'A'
t
WR
2654 drw 13
(3)
(3)
(2)
(4)
Left or Right Port
(1)
Function
R/
W
CE
OE
D
0-8
X
H
X
Z
Port Disable and in Power-Down Mode, I
SB2
or I
SB4
X
H
X
Z
CE
R
=
CE
L
= H, Power-DownMode, I
SB1
or I
SB3
L
L
X
DATA
IN
Data on Port Written Into Memory
(2)
H
L
L
DATA
OUT
Data in Memory Output on Port
(3)
H
L
H
Z
High-Impedance Outputs
2654 tbl 13
Left Port
Right Port
Function
R/
W
L
CE
L
OE
L
A
10L
-A
0L
INT
L
R/
W
R
CE
R
OE
R
A
10R
-A
0R
INT
R
L
L
X
7FF
X
X
X
X
X
L
(2)
Set Right
INT
R
Flag
X
X
X
X
X
X
L
L
7FF
H
(3)
Reset Right
INT
R
Flag
X
X
X
X
L
(3)
L
L
X
7FE
X
Set Left
INT
L
Flag
X
L
L
7FE
H
(2)
X
X
X
X
X
Reset Left
INT
L
Flag
2654 tbl 14
NOTES:
.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interupt Truth Table.
3. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
4. Timing depends on which enable signal (
CE
or R/
W
) is de-asserted first.
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