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| 型號： | IDT70121S45JGI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 高速2K × 9雙端口靜態(tài)RAM繁忙 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70121S45JGI |
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
AC Elec tric al Charac teristic s Over the Operating Temperature
and Supply Voltage Range
(6)
APRIL 05, 2006
NOTES
:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to “Timng Waveformof Write with Port-to-Port Read and
BUSY
.
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual) or t
DDD
– t
DW
(actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. 'X' in part numbers indicates power rating (S or L).
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Unit
BUSY
TIMING (For MASTER IDT70121)
t
BAA
BUSY
Access Time fromAddress
____
20
____
20
ns
t
BDA
BUSY
Disable Time fromAddress
____
20
____
20
ns
t
BAC
BUSY
Access Time fromChip Enable
____
20
____
20
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
20
____
20
ns
t
WDD
Write Pulse to Data Delay
(1)
50
60
t
DDD
Write Data Valid to Read Data Delay
(1)
35
45
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
30
____
30
ns
t
WH
Write Hold After
BUSY
(5)
15
____
20
____
ns
BUSY
INPUT TIMING (For SLAVE IDT70125)
t
WB
Write to
BUSY
Input
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
60
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45
ns
2654 tbl 11a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Unit
BUSY
TIMING (For MASTER IDT 70121)
t
BAA
BUSY
Access Time fromAddress
____
20
____
30
ns
t
BDA
BUSY
Disable Time fromAddress
____
20
____
30
ns
t
BAC
BUSY
Access Time fromChip Enable
____
20
____
30
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
20
____
30
ns
t
WDD
Write Pulse to Data Delay
(1)
70
80
t
DDD
Write Data Valid to Read Data Delay
(1)
55
65
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
35
____
45
ns
t
WH
Write Hold After
BUSY
(5)
20
____
20
____
ns
BUSY
INPUT TIMING (For SLAVE IDT 70125)
t
WB
Write to
BUSY
Input
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
70
____
80
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
55
____
65
ns
2654 tbl 11b
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|---|---|
| IDT70121S45L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70121S45L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70121S55J | 功能描述:IC SRAM 18KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT70121S55J8 | 功能描述:IC SRAM 18KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT70121S55JG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
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