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參數(shù)資料
| 型號(hào)： | IDT70121S35JG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 2K X 9 DUAL-PORT SRAM, 35 ns, PQCC52 |
| 封裝： | 0.75 X 0.75 INCH, 0.17 INCH HEIGHT, GREEN, PLASTIC, LCC-52 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70121S35JG |
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
AC Elec tric al Charac teristic s Over the
Operating Temperature and S upply Voltage Range
(4)
APRIL 05, 2006
NOTES:
1. Transition is measured 0mV fromLow or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, t
WC
= t
BAA
+ t
WP,
since R/W
= V
IL
must occur after t
BAA
.
4. 'X' in part numbers indicates power rating (S or L).
5. The specified t
DH
must be met by the device supplying write date to the RAMunder all operating conditions.
Although t
DH
and
t
OW
values will vary over voltage and temperature. The actual t
DH
will always be smaller than the actual t
OW.
6. If
OE
is LOW during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be
placed on the bus for the required t
DW
. If
OE
is HIGH during a R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
WP
.
Symbol
Parameter
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Unit
Min.
Max.
Mn.
Max.
WRITE CYCLE
t
WC
Write Cycle Time
(4)
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write
20
____
30
____
ns
t
AW
Address Valid to End-of-Write
20
____
30
____
ns
t
AS
Address Set-up Time
0
____
0
____
ns
t
WP
Write Pulse Width
(6)
20
____
30
____
ns
t
WR
Write Recovery Time
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
12
____
20
____
ns
t
HZ
Output High-Z Time
(1,2,3)
____
10
____
15
ns
t
DH
Data Hold Time
(5)
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,3)
____
10
____
15
ns
t
OW
Output Active fromEnd-of-Write
(1,2,3,5)
0
____
0
____
ns
2654 tbl 10a
Symbol
Parameter
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Unit
Min.
Max.
Mn.
Max.
WRITE CYCLE
t
WC
Write Cycle Time
(4)
45
____
55
____
ns
t
EW
Chip Enable to End-of-Write
35
____
40
____
ns
t
AW
Address Valid to End-of-Write
35
____
40
____
ns
t
AS
Address Set-up Time
0
____
0
____
ns
t
WP
Write Pulse Width
(6)
35
____
40
____
ns
t
WR
Write Recovery Time
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
20
____
20
____
ns
t
HZ
Output High-Z Time
(1,2,3)
____
20
____
30
ns
t
DH
Data Hold Time
(5)
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,3)
____
20
____
30
ns
t
OW
Output Active fromEnd-of-Write
(1,2,3,5)
0
____
0
____
ns
2654 tbl 10b
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT70121S35JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
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| IDT70121S35L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70121S45J | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70121S45JG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
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