參數(shù)資料
型號(hào): IDT70121S25J
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
中文描述: 2K X 9 DUAL-PORT SRAM, 25 ns, PQCC52
封裝: 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 168K
代理商: IDT70121S25J
6.10
8
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND
BUSY
(1,2,3)
t
APS
ADDR
'A'
DATA
IN 'A'
MATCH
t
WC
t
WP
R/
W
'A'
ADDR
'B'
DATA
OUT 'B'
MATCH
BUSY
'B'
t
BDA
t
DW
t
DH
VALID
VALID
t
DDD(4)
t
WDD
t
BDD
2654 drw 09
(1)
TIMING WAVEFORM OF WRITE WITH
BUSY
NOTES:
1. tWH must be met for both
BUSY
input (slave) and output (master).
2.
BUSY
is asserted on port 'B' blocking R/
W
'B',
until
BUSY
'B'
goes High.
3. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2654 drw 10
R/
W
'A'
BUSY
'B'
t
WP
t
WB
R/
W
'B'
t
WH
(1)
( 2 )
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for Slave (IDT 70125).
2.
CE
L
=
CE
R
= V
IL
3.
OE
= V
IL
for the reading port.
4.
All
timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
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