參數(shù)資料
型號(hào)： IDT70121L55JG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
中文描述： 2K X 9 DUAL-PORT SRAM, 55 ns, PQCC52
封裝： 0.75 X 0.75 INCH, 0.17 INCH HEIGHT, GREEN, PLASTIC, LCC-52
文件頁(yè)數(shù)： 10/15頁(yè)
文件大?。?/td> 139K
代理商： IDT70121L55JG
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
AC Elec tric al Charac teristic s Over the Operating Temperature
and Supply Voltage Range
(6)
APRIL 05, 2006
NOTES
:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to “Timng Waveformof Write with Port-to-Port Read and
BUSY
.
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual) or t
DDD
– t
DW
(actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. 'X' in part numbers indicates power rating (S or L).
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Unit
BUSY
TIMING (For MASTER IDT70121)
t
BAA
BUSY
Access Time fromAddress
____
20
____
20
ns
t
BDA
BUSY
Disable Time fromAddress
____
20
____
20
ns
t
BAC
BUSY
Access Time fromChip Enable
____
20
____
20
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
20
____
20
ns
t
WDD
Write Pulse to Data Delay
(1)
50
60
t
DDD
Write Data Valid to Read Data Delay
(1)
35
45
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
30
____
30
ns
t
WH
Write Hold After
BUSY
(5)
15
____
20
____
ns
BUSY
INPUT TIMING (For SLAVE IDT70125)
t
WB
Write to
BUSY
Input
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
60
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45
ns
2654 tbl 11a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Unit
BUSY
TIMING (For MASTER IDT 70121)
t
BAA
BUSY
Access Time fromAddress
____
20
____
30
ns
t
BDA
BUSY
Disable Time fromAddress
____
20
____
30
ns
t
BAC
BUSY
Access Time fromChip Enable
____
20
____
30
ns
t
BDC
BUSY
Disable Time fromChip Enable
____
20
____
30
ns
t
WDD
Write Pulse to Data Delay
(1)
70
80
t
DDD
Write Data Valid to Read Data Delay
(1)
55
65
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
35
____
45
ns
t
WH
Write Hold After
BUSY
(5)
20
____
20
____
ns
BUSY
INPUT TIMING (For SLAVE IDT 70125)
t
WB
Write to
BUSY
Input
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
70
____
80
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
55
____
65
ns
2654 tbl 11b
相關(guān)PDF資料
PDF描述
IDT70121L55JGI HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
IDT70121S25JG HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
IDT70121S25JGI Replacement for Harris part number ICL7660SMTV/883B. Buy from authorized manufacturer Rochester Electronics.
IDT70121S35JG HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
IDT70121S35JGI HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT70121L55JGI 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
IDT70121L55L52 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM
IDT70121L55L52B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM
IDT70121L70L52B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM
IDT70121S 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*