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| 型號： | IDT7007L55G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 32K X 8 DUAL-PORT SRAM, 55 ns, CPGA68 |
| 封裝： | 1.800 X 1.800 INCH, 0.160 INCH HEIGHT, PGA-68 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 257K |
| 代理商： | IDT7007L55G |
13
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6,7)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
t
WP
(actual) or t
DDD
t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
Symbol
Parameter
7007X15
Com'l Only
7007X20
Com'l Only
7007X25
Com'l &
Military
Unit
Min.
Max.
Min.
Max.
Min.
Max.
BUSY
TIMING (M/
S
=V
IH
)
t
BAA
BUSY
Access Time from Address Match
____
15
____
20
____
20
ns
t
BDA
BUSY
Disable Time from Address Not Matched
____
15
____
20
____
20
ns
t
BAC
BUSY
Access Time from Chip Enable Low
____
15
____
20
____
20
ns
t
BDC
BUSY
Access Time from Chip Enable High
____
15
____
17
____
17
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
18
____
30
____
30
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
17
____
ns
BUSY
TIMING (M/
S
=V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
45
____
50
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
30
____
35
ns
2940 tbl 14a
Symbol
Parameter
7007X35
Com'l &
Military
7007X55
Com'l, Ind
& Military
Unit
Min.
Max.
Min.
Max.
BUSY
TIMING (M/
S
=V
IH
)
t
BAA
BUSY
Access Time from Address Match
____
20
____
45
ns
t
BDA
BUSY
Disable Time from Address Not Matched
____
20
____
40
ns
t
BAC
BUSY
Access Time from Chip Enable Low
____
20
____
40
ns
t
BDC
BUSY
Access Time from Chip Enable High
____
20
____
35
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
35
____
40
ns
t
WH
Write Hold After
BUSY
(5)
25
____
25
____
ns
BUSY
TIMING (M/
S
=V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
60
____
80
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
45
____
65
ns
2940 tbl 14b
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| IDT7007L55GB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L55GI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
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| IDT7007L55J8 | 功能描述:IC SRAM 256KBIT 55NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7007L55JB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
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