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參數(shù)資料
| 型號(hào)： | IDT7007L25GI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 32K X 8 DUAL-PORT SRAM, 25 ns, CPGA68 |
| 封裝： | 1.800 X 1.800 INCH, 0.160 INCH HEIGHT, PGA-68 |
| 文件頁(yè)數(shù)： | 19/21頁(yè) |
| 文件大?。?/td> | 257K |
| 代理商： | IDT7007L25GI |
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IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7007 in a separate
memory space from the Dual-Port RAM. This address space s accessed
by placing a LOW input on the
SEM
pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address,
OE
, and
R/
W
) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A
0
A
2
. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D
0
is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which s able to write a zero nto a semaphore subsequently ocks out writes
from the other side s what makes semaphore flags useful n nterprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one sides output
register when that side's semaphore select (
SEM
) and output enable (
OE
)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (
SEM
or
OE
) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request atch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Truth
Table V). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that t has written successfully to that ocation and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used nstead, system contention problems could have occurred during the
gap between the read and write cycles.
It s mportant to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force ts side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request atch. Should the other sides semaphore request atch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first sides request
latch. The second sides flag will now stay low until its semaphore request
latch s written to a one. From this t s easy to understand that, f a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta-
neous requests are made, the ogic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the
first side to make the request will receive the token. If both requests arrive
at the same time, the assignment will be arbitrarily made to one port or
Figure 4. IDT7007 Semaphore Logic
the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, f semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
Using SemaphoresSome Examples
Perhaps the simplest application of semaphores s their application as
resource markers for the IDT7007s Dual-Port RAM. Say the 32K x 8 RAM
was to be divided into two 16K x 8 blocks which were to be dedicated at
any one time to servicing either the left or right port. Semaphore 0 could
be used to indicate the side which would control the lower section of
memory, and Semaphore 1 could be defined as the indicator for the upper
section of memory.
To take a resource, in this example the lower 16K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 16K. Meanwhile the right processor was attempting to gain control
of the resource after the eft processor, t would read back a one n response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 16K section
by writing, then reading a zero nto Semaphore 1. If t succeeded n gaining
control, it would lock out the left side.
D
2940 drw 20
0
D
Q
WRITE
D
0
WRITE
D
Q
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
L PORT
R PORT
SEMAPHORE
READ
SEMAPHORE
READ
,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7007L25J | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L25JB | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L25JI | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L25PF | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L25PFB | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7007L25J | 功能描述:IC SRAM 256KBIT 25NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7007L25J8 | 功能描述:IC SRAM 256KBIT 25NS 68PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7007L25JB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L25JI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM |
| IDT7007L25PF | 功能描述:IC SRAM 256KBIT 25NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
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