參數(shù)資料
型號(hào): IDT7007L15PFB
廠商: Integrated Device Technology, Inc.
英文描述: ER 6C 6#16S PIN RECP
中文描述: 高速32K的× 8雙端口靜態(tài)RAM
文件頁(yè)數(shù): 9/21頁(yè)
文件大?。?/td> 257K
代理商: IDT7007L15PFB
9
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is de-asserted first
CE
or
OE
.
3. t
BDD
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
t
RC
R/
W
CE
ADDR
t
AA
t
ACE
OE
2940 drw 07
(4)
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
2940 drw 08
t
PU
I
CC
I
SB
t
PD
,
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