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參數資料
| 型號： | IDT6167SA15Y |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS STATIC RAM 16K (16K x 1-BIT) |
| 中文描述： | 16K X 1 STANDARD SRAM, 15 ns, PDSO20 |
| 封裝： | 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOJ-20 |
| 文件頁數： | 7/8頁 |
| 文件大?。?/td> | 63K |
| 代理商： | IDT6167SA15Y |
5.2
7
IDT6167SA/LA
CMOS STATIC RAM 16K (16K x 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (
WE
CONTROLLED TIMING)
(1, 2, 4)
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
CS
CONTROLLED TIMING)
(1, 2, 4)
NOTES:
1.
WE
or
CS
must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. If the
CS
low transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured
±
200mV from steady state.
6. During this period, the I/O pins are in the output state and the input signals must not be applied.
CS
2981 drw 08
t
AW
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
OW
t
AS
DATA
IN
VALID
(5)
PREVIOUS DATA
OUT
VALID
(6)
DATA
OUT
VALID
(6)
(3)
t
WHZ(5)
t
CHZ(5)
t
WR
CS
2981 drw 09
t
AW
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH
t
AS
DATA
IN
VALID
(3)
相關PDF資料 |
PDF描述 |
|---|---|
| IDT6167SA20D | CMOS STATIC RAM 16K (16K x 1-BIT) |
| IDT6167LA100D | CMOS STATIC RAM 16K (16K x 1-BIT) |
| IDT6167LA100DB | CMOS STATIC RAM 16K (16K x 1-BIT) |
| IDT6167LA100P | CMOS STATIC RAM 16K (16K x 1-BIT) |
| IDT6167LA100PB | CMOS STATIC RAM 16K (16K x 1-BIT) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT6167SA15YB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CMOS STATIC RAM 16K (16K x 1-BIT) |
| IDT6167SA20D | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CMOS STATIC RAM 16K (16K x 1-BIT) |
| IDT6167SA20DB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CMOS STATIC RAM 16K (16K x 1-BIT) |
| IDT6167SA20EB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| IDT6167SA20F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
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