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參數(shù)資料
| 型號(hào)： | IDT5V9955 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Scan Test Devices With 18-Bit Bus Transceivers And Registers 64-LQFP -40 to 85 |
| 中文描述： | 3.3V的可編程相偏雙PLL時(shí)鐘驅(qū)動(dòng)器TURBOCLOCK糯 |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | IDT5V9955 |
3
INDUSTRIAL TEMPERATURE RANGE
IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
NOTE:
1. Capacitance applies to all inputs except TEST, xFS, xnF
[1:0]
, and xDS
[1:0]
.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
Description
C
IN
Input Capacitance
Typ.
8
5
Max.
10
7
Unit
pF
REF
Others
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAX IMUM RATINGS
(1)
Symbol
Description
V
DDQ
, V
DD
Supply Voltage to Ground
V
I
DC Input Voltage
REF Input Voltage
MaximumPower
Dissipation
T
STG
Storage Temperature Range
Max
Unit
V
V
V
W
–0.5 to +4.6
–0.5 to V
DD
+0.5
–0.5 to +5.5
1.1
1.9
–65 to +150
T
A
= 85°C
T
A
= 55°C
°C
NOTE:
1. When TEST = MID and x
sOE
= HIGH, PLL remains active
with xnF[
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain
in effect unless xnF[
1:0
] = LL.
PIN DESCRIPTION
Pin Name
REF
xFB
TEST
(1)
Type
IN
IN
IN
Description
Reference Clock Input
Individual Feedback Inputs for A and B banks
When MID or HIGH, disables PLL for A and B banks (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See
Control Summary Table) remain in effect. Set LOW for normal operation.
Individual Synchronous Output Enable for A and B banks. When HIGH, it stops clock outputs (except x2Q
0
and x2Q
1
) in a LOW state
(for xPE = H) - x2Q
0
and x2Q
1
may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and
sOE
is HIGH, the nF[
1:0
] pins act as output disable controls for individual banks when xnF[
1:0
] = LL. Set x
sOE
LOW for normal operation
(has internal pull-down).
Individual Selectable positive or negative edge control for A and B banks. When LOW/HIGH the outputs are synchronized with the negative/
positive edge of the reference clock (has internal pull-up).
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Individual control on A
and B banks.
Eight banks of two outputs with programmable skew
3-level inputs for feedback divider selection for A and B banks
Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up).
x
sOE
(1)
IN
xPE
IN
xnF
[1:0]
xFS
IN
IN
xnQ
[1:0]
xDS
[1:0]
x
PD
OUT
IN
IN
xLOCK
OUT
PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be
synchronized to the inputs.
Power supply for output buffers
Power supply for phase locked loop, lock output, and other internal circuitry
Ground
V
DDQ
V
DD
GND
PWR
PWR
PWR
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