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參數(shù)資料
| 型號(hào)： | IDT5V9950PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Scan Test Devices With 18-Bit Bus Transceivers And Registers 64-LQFP -40 to 85 |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 67K |
| 代理商： | IDT5V9950PFI |
8
INDUSTRIAL TEMPERATURE RANGE
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
REF
FB
Q
OTHER Q
INVERTED Q
REF DIVIDED BY 2
REF DIVIDED BY 4
t
REF
t
SKEW2
t
SKEW3, 4
t
SKEW1, 3, 4
t
SKEW2, 4
t
SKEW3, 4
t
SKEW3, 4
t
SKEW2
t
SKEWPR
t
SKEW0, 1
t
CCJH,M,L
t
ODCV
t
ODCV
t
RPWH
t
RPWL
t
SKEWPR
t
SKEW0, 1
t
(
φ)
AC TIMING DIAGRAM
NOTES:
PE:
The AC Timng Diagramapplies to PE=V
DD
. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
The time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are loaded with 20pF and termnated
with 75
to V
DDQ
/2.
The skew between a pair of outputs (xQ
0
and xQ
1
) when all eight outputs are selected for 0t
U
.
The skew between outputs when they are selected for 0t
U
.
The output-to-output skew between any two devices operating under the same conditions (V
DDQ
,
V
DD
, ambient temperature, air flow, etc.)
The deviation of the output froma 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
specifications.
t
PWH
is measured at 2V.
t
PWL
is measured at 0.8V.
t
ORISE
and t
OFALL
are measured between 0.8V and 2V.
t
LOCK
:
The time that is required before synchronization is achieved. This specification is valid only after V
DD
/V
DDQ
is stable and within normal operating limts. This parameter
is measured fromthe application of a new signal or frequency at REF or FB until t
PD
is within specified limts.
Skew:
t
SKEWPR
:
t
SKEW0
:
t
DEV
:
t
ODCV
:
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