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參數資料
| 型號： | IDT5V49EE704NDGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 28/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 200MHZ 28VFQFPN |
| 產品培訓模塊： | VersaClock™ III Programmable Clocks |
| 特色產品： | VersaClock III Timing Devices |
| 標準包裝： | 75 |
| 系列： | VersaClock™ III |
| 類型： | 時鐘發(fā)生器，多路復用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:7 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-VFQFPN（4x4） |
| 包裝： | 管件 |
| 其它名稱： | 800-1917 IDT5V49EE704DLGI |
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IDT5V49EE704
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
8
IDT5V49EE704
REV M 092412
SS_OFFSET[5:0]
These bits are used to program the fractional offset with
respect to the nominal M integer value. For center spread,
the SS_OFFSET is set to '0' so that the spread spectrum
waveform is centered about the nominal M (Mnom) value.
For down spread, the SS_OFFSET > '0' such the spread
spectrum waveform is centered about the (Mideal -1
+SS_Offset) value. The downspread percentage can be
thought of in terms of center spread. For example, a
downspread of -1% can also be considered as a center
spread of ±0.5% but with Mnom shifted down by one and
offset. The SS_OFFSET has integer values ranging from 0
to 63.
SD[3:0]
These bits are used to shape the profile of the spread
spectrum waveform. These are delta-encoded samples of
the waveform. There are twelve sets of SD samples. The
NSSC bits determine how many of these samples are used
for the waveform. The sum of these delta-encoded samples
(sigma delta- encoded samples) determine the amount of
spread and should not exceed (63 - SS_OFFSET). The
maximum spread is inversely proportional to the nominal M
integer value.
DITH
This bit is used for dithering the sigma-delta-encoded
samples. This will randomize the least-significant bit of the
input to the spread spectrum modulator. Set the
bit to '1' to
enable dithering.
X2
This bit will double the total value of the
sigma-delta-encoded-samples which will increase the
amplitude of the spread spectrum waveform by a factor of
two. When X2 is '0', the amplitude remains nominal but if set
to '1', the amplitude is increased by x2. The following
equations govern how the spread spectrum is set:
TSSC = TSSC[3:0] + 2 (Eq. 2)
NSSC = NSSC[2:0] * 2 (Eq. 3)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 4)
where SJ is the unencoded sample out of a possible 12 and
SDK is the delta-encoded sample out of a possible 12.
Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2
(Eq. 5)
if 1 < Amplitude < 2, then set X2 bit to '1'.
Modulation frequency:
FPFD = FIN / D (Eq. 6)
FVCO = FPFD * MNOM (Eq. 7)
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 8)
Spread:
ΣΔ = SD0 + SD1 + SD2 + …+ SD11
the number of samples used depends on the NSSC value
ΣΔ< 63 - SS_OFFSET
±Spread% =
(
ΣΔ * 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9)
±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT5V49EE704NDGI8 | 功能描述:IC PLL CLK GEN 200MHZ 28VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V49EE901-064PGGI | 制造商:Integrated Device Technology Inc 功能描述:IC PLL CLK GEN 500MHZ 24VQFN |
| IDT5V49EE901-064PGGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL CLK GEN 500MHZ 24VQFN |
| IDT5V49EE901-EVB | 制造商:Integrated Device Technology Inc 功能描述:EVAL BOARD FOR IDT 5V49EE901 |
| IDT5V49EE901NLGI | 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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