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參數(shù)資料
| 型號(hào)： | IDT5V19EE604NDGI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 24/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 200MHZ 28VFQFPN |
| 特色產(chǎn)品： | VersaClock III Timing Devices |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | VersaClock™ III |
| 類型： | 時(shí)鐘發(fā)生器，多路復(fù)用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-VFQFPN（4x4） |
| 包裝： | 帶卷 (TR) |
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IDT5V19EE604
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
4
IDT5V19EE604
REV M 092412
12
OUT5b
O
LVTTL1
Configurable clock output 5b. Output levels controlled by
VDDO5.
13
VDDO5
Power
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT5 and OUT5b.
14
GND
Power
Connect to Ground.
15
SDAT
I/O
Open Drain
Bidirectional I2C data. An external pull-up resistor is
required. See I2C specification for pull-up value
recommendation.
16
SCLK
I
LVTTL
I2C clock. An external pull-up resistor is required. See
I2C specification for pull-up value recommendation.
17
CLKSEL
I
LVTTL
Input clock selector. Weak internal pull down resistor.
18
AVDD
Power
Device analog power supply. Connect to 3.3V. Use
filtered analog power supply if available.
19
GND
Power
Connect to Ground.
20
OUT6
O
LVTTL
Configurable clock output 6. Output levels controlled by
VDDO3.
21
OUT3
O
LVTTL
Configurable clock output 3. Output levels controlled by
VDDO3.
22
VDDO3
Power
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT3 and OUT6.
23
SEL2
I
LVTTL
Configuration select pin. Weak internal pull down
resistor.
24
SEL1
I
LVTTL
Configuration select pin. Weak internal pull down
resistor.
25
SEL0
I
LVTTL
Configuration select pin. Weak internal pull down
resistor.
26
SD/OE
I
LVTTL
Enables/disables the outputs or powers down the chip.
The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW. (Default is active LOW.)
Weak internal pull down resistor.
27
GND
Power
Connect to Ground.
28
VDD
Power
Device power supply. Connect to 3.3V.
1.When only an individual single-ended clock output is required, tie OUT# and OUT#b together.
2. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
3. Each power pin should have a dedicated 0.01F de-coupling capacitor. Digital VDDs may be tied together.
4. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
Pin#
Pin Name
I/O
Pin Type
Pin Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V19EE901NLGI | 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V19EE901NLGI8 | 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V19EE901PGGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR |
| IDT5V19EE901PGGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN VCXO PROGR 28TSSOP |
| IDT5V19EE902-EVB | 制造商:Integrated Device Technology Inc 功能描述:EVAL BOARD FOR IDT 5V19EE902 |
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