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參數資料
| 型號： | IDT5T9950PFI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 81K |
| 代理商： | IDT5T9950PFI8 |
1
INDUSTRIALTEMPERATURERANGE
IDT5T9950/A
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
FEBRUARY 2002
2002
Integrated Device Technology, Inc.
DSC 5869/6
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Ref input is 3.3V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency:
– Std: 6MHz to 160MHz
– A: 6MHz to 200MHz
Output frequency:
– Std: 6MHz to 160MHz
– A: 6MHz to 200MHz
2x, 4x, 1/2, and 1/4 outputs
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Standard and A speed grades
Available in TQFP package
FUNCTIONAL BLOCK DIAGRAM
sO E
1Q0
Skew
Select
1Q1
1F1:0
3
2Q0
Skew
Select
2Q1
2F1:0
FS
3
RE F
PLL
FB
3
3Q0
Skew
Select
3Q1
3F1:0
3
4Q0
4Q1
Skew
Select
4F1:0
3
PE TE ST
3
IDT5T9950/A
2.5V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK II JR.
DESCRIPTION:
The IDT5T9950 is a high fanout 2.5V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5T9950 has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate high-mid-low levels.
When the
sOE pin is held low, all the outputs are synchronously enabled.
However, if
sOE is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled. The LOCK output asserts to indicate when Phase
Lock has been achieved.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5T9950 has
LVTTL outputs with 12mA balanced drive outputs.
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