JTAG/ I2
參數(shù)資料
型號(hào): IDT5T9820NLGI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 34/36頁(yè)
文件大小: 0K
描述: IC CLK DRIVER ZD PLL 68-VFQFPN
產(chǎn)品變化通告: Product Discontinuation 05/Jan/2011
標(biāo)準(zhǔn)包裝: 168
類型: PLL 時(shí)鐘驅(qū)動(dòng)器
PLL: 帶旁路
輸入: eHSTL,HSTL,LVPECL,LVTTL
輸出: eHSTL,HSTL,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:10
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 250MHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.3 V ~ 2.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 68-VFQFPN(10x10)
包裝: 托盤(pán)
其它名稱: 5T9820NLGI
7
INDUSTRIALTEMPERATURERANGE
IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
JTAG/ I2C SERIAL DESCRIPTION, CONT.
Bit
Description
20
Divide selection for bank 2
19
Divide selection for bank 3
18
Divide selection for bank 3
17
Divide selection for bank 3
16
Divide selection for bank 3
15
Divide selection for bank 3
14
Divide selection for bank 4
13
Divide selection for bank 4
12
Divide selection for bank 4
11
Divide selection for bank 4
10
Divide selection for bank 4
9
Divide selection for bank 5
8
Divide selection for bank 5
7
Divide selection for bank 5
6
Divide selection for bank 5
5
Divide selection for bank 5
4
Divide selection for FB bank
3
Divide selection for FB bank
2
Divide selection for FB bank
1
Divide selection for FB bank
0
Divide selection for FB bank
JTAG/ I2C SERIAL CONFIGURATIONS:
OUTPUTENABLE/DISABLE
Bit 59 (OMODE)
Bit 56-52 (nsOE)
Output
X(X)
0 and (L)
NormalOperation
0 and (L)
1 or (H)
Tri-Sate
1 or (H)
Gated(1)
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the
QFB is stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding
Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I2C SERIAL CONFIGURATIONS:
POWERDOWN
PD
Bit 59 (OMODE)
Output
H
X(X)
NormalOperation
L
0 and (L)
Tri-Sate
L
1 or (H)
Gated(1)
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the
QFB is stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding
Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I2C SERIAL CONFIGURATIONS:
CLOCK INPUT INTERFACE SELEC-
TION(1)
Bit 31, 33, 35
Bit 30, 32, 34
Interface
0
Differential(2)
0
1
2.5VLVTTL
1
1.8VLVTTL
NOTES:
1. All other states that are undefined in the table will be reserved.
2. Differential input interface for HSTL/eHSTL, LVEPECL (2.5V), and 2.5V/1.8V LVTTL.
JTAG/ I2C SERIAL CONFIGURATIONS:
OUTPUT DRIVE STRENGTH
SELECTION(1)
Bit 37, 39, 41,
Bit 36, 38, 40,
43, 45, 47
42, 44, 46
Interface
0
2.5VLVTTL
0
1
1.8VLVTTL
1
0
HSTL/eHSTL
NOTE:
1. All other states that are undefined in the table will be reserved.
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