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參數(shù)資料
| 型號(hào)： | IDT5T915PAI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER |
| 中文描述： | 5T SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大?。?/td> | 127K |
| 代理商： | IDT5T915PAI |
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INDUSTRIAL TEMPERATURE RANGE
12
IDT5T915
2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER
AC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE
(5)
Symbol
Parameter
Skew Parameters
t
SK
(
O
)
Same Device Output Pin-to-Pin Skew
(1)
Min.
Typ.
Max
Unit
Single-Ended and Differential Modes
Single-Ended in Differential Mode (DSE)
Single-Ended and Differential Modes
Single-Ended in Differential Mode (DSE)
Single-Ended and Differential Modes
Single-Ended in Differential Mode (DSE)
Single-Ended and Differential Modes
Single-Ended in Differential Mode (DSE)
—
—
—
—
—
—
—
—
—
25
—
300
—
300
—
300
V
DDQ
/2
25
—
300
—
300
—
300
—
ps
t
SK
(
INV
)
Inverting Skew
(2)
ps
t
SK
(
P
)
Pulse Skew
(3)
ps
t
SK
(
PP
)
Part-to-Part Skew
(4)
ps
V
OX
HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level
V
DDQ
/2 - 200
V
DDQ
/2 + 200
mV
Propagation Delay
t
PLH
t
PHL
t
R
Propagation Delay A to Qn/
Qn
2.5V / 1.8V LVTTL Outputs
HSTL / eHSTL Outputs
2.5V / 1.8V LVTTL Outputs
HSTL / eHSTL Outputs
2.5V / 1.8V LVTTL Outputs
HSTL / eHSTL Outputs
—
—
350
350
350
350
—
—
—
—
—
—
—
—
—
—
2.5
2
1050
1350
1050
1350
250
200
ns
Output Rise Time (20% to 80%)
ps
t
F
Output Fall Time (20% to 80%)
ps
f
O
Frequency Range (HSTL/eHSTL outputs)
Frequency Range (2.5V/1.8V LVTTL outputs)
MHz
Output Gate Enable/Disable Delay
t
PGE
t
PGD
Output Gate Enable to Qn/
Qn
Output Gate Enable to Qn/
Qn
Driven to GL Designated Level
—
—
—
—
3.5
3
ns
ns
NOTES:
1. Skew measured between all outputs or output pairs under identical input and output interfaces, transitions and load conditions on any one device. For single ended and differential
LVTTL outputs, this measurement is made when each output voltage passes through V
DDQ
/2. For differential LVTTL outputs, the true outputs are compared only with other true
outputs and the complementary outputs are compared only with other complementary outputs. For differential HSTL outputs, the measurement takes place at the crossing point
of the true and complementary signals.
2. For operating with either 1.8V or 2.5V LVTTL output interfaces with both true and complementary outputs enabled. Inverting skew is the skew between true and complementary
outputs switching in opposite directions under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times t
PHL
and t
PLH
of any output or output pair under identical input and output interfaces, transitions and load conditions
on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through V
DDQ
/2. The measurement applies
to both true and complementary signals. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals.
4. Skew measured is the magnitude of the difference in propagation times between any outputs or output pairs of two devices, given identical transitions and load conditions at identical
V
DD
/V
DDQ
levels and temperature.
5. Guaranteed by design.
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