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參數(shù)資料
| 型號(hào)： | IDT54FCT825BTD |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| 中文描述： | 高性能CMOS總線接口寄存器 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 178K |
| 代理商： | IDT54FCT825BTD |
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.21
8
PULSE WIDTH
SWITCH POSITION
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2567 drw 05
2567 drw 06
2567 drw 07
2567 drw 08
2567 drw 09
2567 lnk 10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT54FCT825BTDB | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| IDT54FCT825BTE | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| IDT54FCT825BTEB | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| IDT54FCT821CT | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| IDT54FCT821CTD | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
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