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參數(shù)資料
| 型號(hào)： | IDT54FCT823ADB8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, 9-BIT DRIVER, TRUE OUTPUT, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 89K |
| 代理商： | IDT54FCT823ADB8 |
MILITARYANDCOMMERCIAL TEMPERATURERANGES
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
54/74FCT823A
54FCT823B
74FCT823C
Com'l.
Mil.
Com'l.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
PropagationDelay
CL = 50pF
—
10
—
11.5
—
8.5
—
6
ns
tPHL
CP to Yx (OE = LOW)
RL = 500
CL = 300pF(3)
—
20
—
20
—
16
—
12.5
RL = 500
tPZH
OutputEnableTime,
CL = 50pF
—
12
—
13
—
9
—
7
ns
tPZL
OE to Yx
RL = 500
CL = 300pF(3)
—
23
—
25
—
16
—
12.5
RL = 500
tPHZ
OutputDisableTime,
CL = 5pF(3)
—
7
—
8
—
7
—
6.2
ns
tPLZ
OE to Yx
RL = 500
CL = 50pF
—
8
—
9
—
8
—
6.5
RL = 500
tSU
Set-up Time HIGH or LOW, Dx to CP
CL = 50pF
4
—
4
—
3
—
3
—
ns
Set-up Time HIGH or LOW, EN to CP
RL = 500
tH
Hold Time HIGH or LOW, Dx to CP
2
—
2
—
1.5
—
1.5
—
ns
tH
Hold Time HIGH or LOW, EN to CP
2
—
2
—
0
—
0
—
ns
tPHL
Propagation Delay, CLR to Yx
—
14
—
15
—
9.5
—
8
ns
tREM
Recovery Time, CLR to CP
6
—
7
—
6
—
6
—
ns
tW
CP Pulse Width HIGH or LOW
7
—
7
—
6
—
6
—
ns
tW
CLR Pulse Width HIGH or LOW
6
—
7
—
6
—
6
—
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
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