參數(shù)資料
型號(hào)： IDT54FCT273TLB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 通用總線功能
英文描述： FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
中文描述： FCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20
封裝： LCC-20
文件頁(yè)數(shù)： 6/7頁(yè)
文件大?。?/td> 109K
代理商： IDT54FCT273TLB
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
6.10
6
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
2568 drw 04
2568 drw 05
2568 drw 06
2568 drw 07
2568 drw 08
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2568 lnk 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
相關(guān)PDF資料
PDF描述
IDT74FCT273TLB FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT54FCT273TSO FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT74FCT273TSO FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT54FCT273TD FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT74FCT273TD FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
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