參數(shù)資料
型號(hào)： IDT54FCT273TD
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通用總線功能
英文描述： FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
中文描述： FCT SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20
封裝： CERDIP-20
文件頁(yè)數(shù)： 5/7頁(yè)
文件大?。?/td> 109K
代理商： IDT54FCT273TD
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.10
5
IDT54/74FCT273T
IDT54/74FCT273AT
IDT54/74FCT273CT
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
Parameter
Condition
(1)
CL = 50pF
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Min.
(2)
Max.
Unit
Propagation Delay
CP to O
N
RL = 500
2.0
13.0
2.0
15.0
2.0
7.2
2.0
8.3
2.0
5.8
2.0
6.5
ns
t
PHL
Propagation Delay
MR
to O
N
Set-up Time HIGH or LOW
D
N
to CP
Hold Time HIGH or LOW D
N
to CP
CP Pulse Width HIGH or
LOW
MR
Pulse Width LOW
2.0
13.0
2.0
15.0
2.0
7.2
2.0
8.3
2.0
6.1
2.0
6.8
ns
t
SU
3.0
—
3.5
—
2.0
—
2.0
—
2.0
—
2.0
—
ns
t
H
2.0
—
2.0
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
t
W
7.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
t
W
7.0
—
7.0
—
6.0
—
6.0
—
6.0
—
6.0
—
ns
t
REM
Recovery Time
MR
to CP
4.0
—
5.0
—
2.0
—
2.5
—
2.0
—
2.5
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2568 tbl 07
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
相關(guān)PDF資料
PDF描述
IDT74FCT273TD FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT54FCT273TE FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT74FCT273TE FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT54FCT273AT Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 0.1uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-20%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 1825; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.180" x 0.250" x 0.080"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate
IDT54FCT273ATD FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
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