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參數資料
| 型號： | IDT54FCT2645CTLB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | CAP 0.068UF 50V 10% X7R SMD-1206 TR-7-PL SN-NIBAR |
| 中文描述： | FCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CQCC20 |
| 封裝： | LCC-20 |
| 文件頁數： | 7/8頁 |
| 文件大小： | 157K |
| 代理商： | IDT54FCT2645CTLB |
IDT54/74FCT245T/AT/CT/DT - 2245T/AT/CT, IDT54/74FCT640T/AT/CT, IDT54/74FCT645T/AT/CT/DT
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.9
7
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Open Drain
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2534 drw 04
2534 drw 05
2534 drw 06
2534 drw 07
2534 drw 08
2534 lnk 14
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