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參數(shù)資料
| 型號： | IDT54FCT2374TDB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | FAST CMOS OCTAL D REGISTERS (3-STATE) |
| 中文描述： | FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 168K |
| 代理商： | IDT54FCT2374TDB |
IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.13
3
PIN DESCRIPTION
FUNCTION TABLE
(1)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
V
TERM(2)
Terminal Voltage
with Respect to
GND
V
TERM(3)
Terminal Voltage
with Respect to
GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
P
T
Power Dissipation
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
–0.5 to
V
CC
+0.5
–0.5 to
V
CC
+0.5
V
0 to +70
–55 to +125
°
C
–55 to +125
–65 to +135
°
C
–55 to +125
–65 to +150
°
C
0.5
0.5
W
I
OUT
DC Output
Current
–60 to +120 –60 to +120 mA
2569 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
2569 lnk 03
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
NC = No Change
↑
= LOW-to-HIGH transition
2569 tbl 02
NOTE:
1. This parameter is measured at characterization but not tested.
2569 lnk 04
Conditions
V
IN
= 0V
Typ.
6
Max. Unit
10
pF
V
OUT
= 0V
8
12
pF
Pin Names
D
N
CP
Description
D flip-flop data inputs
Clock Pulse for the register. Enters data on
LOW-to-HIGH transition.
3-state outputs, (true)
Q
N
Q
N
3-state outputs, (inverted)
Active LOW 3-state Output Enable input
OE
534
374/574
Inputs
CP
L
H
↑
↑
↑
↑
Outputs
Internal
Q
N
NC
NC
L
H
L
H
Outputs
Q
N
Z
Z
L
H
Z
Z
Internal
Function
OE
H
H
L
L
H
H
D
N
X
X
L
H
L
H
Q
N
Z
Z
H
L
Z
Z
Q
N
NC
NC
H
L
H
L
HI-Z
LOAD REGISTER
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