參數(shù)資料
型號: IDT54FCT162260ETPVB
廠商: Integrated Device Technology, Inc.
英文描述: CAP 2.2UF 50V 20% TANT SMD-6032-28 TR-7-PL SN100% LOWESR-1500
中文描述: 快速CMOS 12位的三端口總線交換
文件頁數(shù): 6/8頁
文件大小: 132K
代理商: IDT54FCT162260ETPVB
5.4
6
IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
3032 tbl 10
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
FCT16260AT/162260AT
FCT16260CT/162260CT
FCT16260ET/162260ET
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Unit
C
L
= 50pF
R
L
= 500
1.5
5.6
1.5
5.9
1.5
5.0
Propagation Delay
A
X
to 1B
X
or Ax to 2B
X
Propagation Delay
1B
X
to A
X
or 2B
X
to A
X
Propagation Delay
LE
X
B to A
X
Propagation Delay
LEA1B to 1B
X
or
LEA2B to 2B
X
Propagation Delay
SEL to A
X
Output Enable Time
OEA
to A
X
,
OE1B
to 1B
X,
or
OE2B
to 2B
X
Output Disable Time
OEA
to A
X
,
OE1B
to 1B
X
, or
OE2B
to 2B
X
Set-Up Time, HIGH or LOW
Data to Latch
Hold Time, Latch to Data
Pulse Width, Latch HIGH
(4)
t
SK
(o) Output Skew
(3)
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
3.6
ns
1.5
5.4
1.5
3.6
ns
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
4.0
ns
1.5
4.7
1.5
5.2
1.5
4.4
1.5
4.8
1.5
4.0
ns
t
PLH
t
PHL
t
PZH
t
PZL
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
4.0
ns
1.5
5.7
1.5
6.1
1.5
5.1
1.5
5.4
1.5
4.4
ns
t
PHZ
t
PLZ
1.5
4.4
1.5
4.8
1.5
4.0
1.5
4.4
1.5
4.0
ns
t
SU
1.5
1.5
1.0
1.0
1.0
ns
t
H
t
W
1.0
3.0
0.5
1.5
3.0
0.5
1.0
3.0
0.5
1.5
3.0
0.5
1.0
3.0
0.5
ns
ns
ns
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